Xilinx ZC706 User Manual

ZC706 Evaluation Board User Guide www.xilinx.com 42
UG954 (v1.5) September 10, 2015
Feature Descriptions
GTX_BANK_110
AH2 MGTPTXP0_110 FMC_HPC_DP4_C2M_P A34
FMC HPC
J37
AH1 MGTPTXN0_110 FMC_HPC_DP4_C2M_N A35
AH6 MGTPRXP0_110 FMC_HPC_DP4_M2C_P A14
AH5 MGTPRXN0_110 FMC_HPC_DP4_M2C_N A15
AF2 MGTPTXP1_110 FMC_HPC_DP5_C2M_P A38
AF1 MGTPTXN1_110 FMC_HPC_DP5_C2M_N A39
AG4 MGTPRXP1_110 FMC_HPC_DP5_M2C_P A18
AG3 MGTPRXN1_110 FMC_HPC_DP5_M2C_N A19
AE4 MGTPTXP2_110 FMC_HPC_DP6_C2M_P B36
AE3 MGTPTXN2_110 FMC_HPC_DP6_C2M_N B37
AF6 MGTPRXP2_110 FMC_HPC_DP6_M2C_P B16
AF5 MGTPRXN2_110 FMC_HPC_DP6_M2C_N B17
AD2 MGTPTXP3_110 FMC_HPC_DP7_C2M_P B32
AD1 MGTPTXN3_110 FMC_HPC_DP7_C2M_N B33
AD6 MGTPRXP3_110 FMC_HPC_DP7_M2C_P B12
AD5 MGTPRXN3_110 FMC_HPC_DP7_M2C_N B13
AA8 MGTREFCLK0P_110 FMC_HPC_GBTCLK1_M2C_P
(1)
B20
AA7 MGTREFCLK0N_110 FMC_HPC_GBTCLK1_M2C_N
(1)
B21
AC8 MGTREFCLK1P_110 SI5324_OUT_C_P
(2)
28
SI5324C
U60
AC7 MGTREFCLK1N_110 SI5324_OUT_C_N
(2)
29
Notes:
1. AP SoC U1 GTX input clock nets are capacitively coupled to the FMC HPC J37 pins.
2. AP SoC U1 GTX input clock nets are capacitively coupled to the SI5324C Recovery Clock U60 output pins.
Table 1-14: AP SoC GTX Banks 109 and 110 Interface Connections to FMC HPC J37 (Cont’d)
Transceiver
Bank
AP SoC U1
Pin
Number
AP SoC U1 Pin Name Schematic Net Name
Connected
Pin
Connected
Device
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Xilinx ZC706 Specifications

General

Brand	Xilinx
Model	ZC706
Category	Motherboard
Language	English