56
S-102
W9864G2GH-7 (IC402: 1U-3836)
PIN DESCRIPTION
PIN NAME FUNCTION DESCRIPTION
A0
−
A10
Address Multiplexed pins for row and column address.
Row address: A0
−
A10. Column address: A0
−
A7.
A10 is sampled during a precharge command to determine if
all banks are to be precharged or bank selected by BS0, BS1.
BS0, BS1 Bank Select
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
DQ0
−
DQ31
Data Input/
Output
Multiplexed pins for data output and input.
CS
Chip Select Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the
clock
RAS
CAS
WE
define the operation to be
executed.
CAS
Column Address
Strobe
Referred to
RAS
WE
RAS
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency.
CLK Clock Inputs System clock used to sample inputs on the rising edge of
clock.
CKE Clock Enable CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
V
CC
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
V
SS
Ground Ground for input buffers and logic circuit inside DRAM.
V
CCQ
I/O buffer
Separated power from V
CC
, to improve DQ noise immunity.
V
SSQ
Ground for I/O
buffer
Separated ground from V
SS
, to improve DQ noise immunity.
NC No Connection No connection
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