HP 1630A User Manual

Model 1630A/D/G
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State Measurements
CLOCK
ASSIGNMENTS
MULTIPLEX ASSIGNMENT
State Format Specification ----------------------------------- _ .
Multi lex
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Pod6
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PodS
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Activity> ____________________ __$IItISit ____IS_IS __1111111
Label Pol
JKL
Clock
Figure 4-3b . 1630G Default State Format Specification
Menu
The logic
analyzer must recognize data on the same clock edge as the target system
when taking state
measurements . Three OR'ed clocksare available in the State [Assignment]
Format Specification . The default
clock assignment specifies to the analyzer to collect data on the positive edge
of the J clock . Other clock
specifications may be made by moving the cursor to the OR'ed clock
field on the assignment menu and
using
the NEXT[] or PREV[] keys to select different clocks and edges .
Some target systems may use
multiplexing in which certain signal lines are used for different
information at
different times .
In
the
target system used for the examples in this manual, the data bits and
eight lower address
bits are
multiplexed on the same pins of the microprocessor . The logic analyzer can
demultiplexthese lines so
the data
and address will be listed in separate columns in the state listing . To set
the multiplexing mode on,
move
the cursor to the field under Multiplex (Multiplexing on 1630 A/D) in the
State [Assignment]Format
Specification and press the NEXT[] or PREV[] key . The multiplex choices are
displayed in ratiosthat indicate
the number of channels to be processed by the slave/master clocks . The
slave clock moves information to a
holding register and the
master clock puts both sets of information into the logic analyzer memory
. When
multiplexing is
on, edges for the master and slave clock are automatically assigned . To
change clock
assignments,
move thecursor to the clock field and use the NEXT[] or PREV[] keys to select
different clocks
and edges .
For the target system used in examples
for
this
manual, the multiplex field is set to [27/16] on the 1630A/D and
to [27/38] on the 1630G . These are the typical settings for 8-bit
microprocessors that multiplex data and
address lines in the same manner as the 8085 . For 16-bit microprocessors
that utilize multiplexed lines,
demultiplexing is usually set at 18 channels for the slave clock instead of
27 .
THRESHOLD ASSIGNMENTS
Input threshold
levels are selectable for each pod . The threshold is selected bymoving the cursor
into the field
under an individual
podand selecting TTL, ECL, or absolutevoltages between-9 .9V and +9 .9V . The
threshold
level
determines whether the incoming voltage will be recorded as a logic 1 (if above
the threshold) or a logic O
(if below the threshold level) .
NOTE
All probe connections within a pod are assigned the same threshold level .
4-5

HP 1630A Specifications

General

Brand	HP
Model	1630A
Category	Measuring Instruments
Language	English