© National Instruments | 6-13
X Series User Manual
Digital Waveform Generation
You can generate digital waveforms on the Port 0 DIO lines. The DO waveform generation
FIFO stores the digital samples. X Series devices have a DMA controller dedicated to moving
data from the system memory to the DO waveform generation FIFO. The DAQ device moves
samples from the FIFO to the DIO terminals on each rising or falling edge of a clock signal, DO
Sample Clock. You can configure each DIO signal to be an input, a static output, or a digital
waveform generation output.
The FIFO supports a retransmit mode. In the retransmit mode, after all the samples in the FIFO
have been clocked out, the FIFO begins outputting all of the samples again in the same order.
For example, if the FIFO contains five samples, the pattern generated consists of sample #1, #2,
#3, #4, #5, #1, #2, #3, #4, #5, #1, and so on.
X Series devices feature the following DO (waveform generation) timing signals:
• DO Sample Clock Signal
*
•
DO Sample Clock Timebase Signal
• DO Start Trigger Signal
*
•
DO Pause Trigger Signal
*
Signals with an
*
support digital filtering. Refer to the
PFI Filters section of Chapter 8, PFI, for
more information.
DO Sample Clock Signal
The device uses the DO Sample Clock (do/SampleClock) signal to update the DO terminals with
the next sample from the DO waveform generation FIFO.
You can specify an internal or external source for DO Sample Clock. You can also specify
whether the DAC update begins on the rising edge or falling edge of DO Sample Clock. If the
DAQ device receives a DO Sample Clock when the FIFO is empty, the DAQ device reports an
underflow error to the host software.
Using an Internal Source
One of the following internal signals can drive DO Sample Clock:
• DI Sample Clock (di/SampleClock)
• DO Sample Clock (do/SampleClock)
• AI Sample Clock (ai/SampleClock)
• AI Convert Clock (ai/ConvertClock)
• AO Sample Clock (ao/SampleClock)
• Counter n Sample Clock
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