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Nvidia Jetson AGX Orin Series User Manual

Nvidia Jetson AGX Orin Series
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USB 3.2 Compliance Test Guide
PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide DA-11040-001_v0.7 | 8
Putting the Orin module USB 3.2 Controller in
Compliance Mode
For Gen1 (5 Gb/p) TX Electrical Tests refer to sections TD.1.1, TD.1.3, and TD.1.4. For Gen2 (10
Gb/s) TX Electrical Tests, refer to sections: TD 1.4, TD 1.5, and TD1.7. These sections can be
found in the
Electrical Compliance Test Specification SuperSpeed Universal Serial Bus
at the
following link: https://www.usb.org/document-
library/electrical-compliance-test-
specification-superspeed-usb-10-gbps-rev-10
Perform the following steps to place the device under test (DUT) into compliance mode:
1. Boot up the DUT. Ensure the USB 3.2 (Gen1 or Gen2) host test fixture is not connected to
the DUT.
2. Install the latest OS (Linux, for example) image for the Orin module.
3. Install the devmem2 tool (for the Linux installed in Step 2, for example) by running the
following command.
$ sudo apt-get install devmem2
4.
Launch the USB 3.2 Compliance Test Software on the scope.
5. Disable the auto suspend for the controllers:
$ echo on > /sys/bus/usb/devices/usb1/power/control
$ echo on > /sys/bus/usb/devices/usb2/power/control
6.
Enter compliance test mode.
$ ./devmem2 0x03610420 w 0x10340
$ ./devmem2 0x03610430 w 0x10340
$ ./devmem2 0x03610440 w 0x10340
Plug in the USB 3.2 host test fixture to DUT. The other end of fixture should be connected to a
scope such that DUT TX+/- with 50 ohm termination on the scope.
For connection details refer to the “Transmitter Test Topologies” section in
USB 3.0 Electrical
Test Fixture Topologies
, at the following link: https://www.usb.org/document-library/usb-31-
electrical-test-fixture-topology
7. Use ./devmem2 0x3610420 (that is, for L0) command to read back the LTSSM state.
Notes: The Orin module contains three USB 3.2 ports.
The PORTSC offset and pin # are:
HS_UPHY0_L0_TX/RX (pins F13/E13/B15/B16), offset = 0x420
HS_UPHY0_L1_TX/RX (pins E12/D12/A14/A15), offset = 0x430
HS_UPHY0_L2_TX/RX (pins F11/E11/B13/B12), offset = 0x440
Writing 0x10340 will change the internal state of XUSB. Therefore, it is not expected to read back
the same value. However, Bits[8:5] should be set to 0xA for compliance test mode, otherwise
repeat Steps 1 through 7.
8. Connect RX+/- to external Ping.LFPS (20 MHz frequency; two periods) signal generator.

Table of Contents

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Nvidia Jetson AGX Orin Series Specifications

General IconGeneral
Memory32GB 256-bit LPDDR5
Storage64GB eMMC 5.1
Networking10/100/1000BASE-T Ethernet
Dimensions100 mm x 87 mm
GPUNVIDIA Ampere architecture with 64 Tensor Cores
CPU12-core Arm Cortex-A78AE v8.2 64-bit CPU
AI Performance275 TOPS
Power15W to 60W
Video Encode2x 4Kp60 | 8x 1080p60 | 16x 1080p30 (H.265/H.264)
USB2x USB 2.0
PCIePCIe Gen 4
Operating System SupportUbuntu

Summary

USB 2.0 Tuning Guide

Tuning Procedure and Registers

Explains calibration based on silicon process and fuse settings.

HS_CURR_LEVEL Offset Adjustment Procedure

Procedure to adjust the HS_CURR_LEVEL register for USB HS eye diagram.

USB 3.2 Compliance Test Guide

USB 3.2 TX and RX Compliance Tests

Guidance on running USB 3.2 TX electrical compliance and RX JTOL tests.

Putting the Orin module USB 3.2 Controller in Compliance Mode

Steps to place the device under test into USB 3.2 compliance mode.

Putting the Orin module USB 3.2 Controller in Loop-Back Mode

Procedure to set the Orin module into loop-back mode for RX testing.

PCIe Compliance Testing Reference

Electrical Characterization

Details the electrical characterization for PCIe compliance testing.

Tx Test

Describes the mechanism and steps for PCIe Tx testing.

HDMI Tuning Guide

DisplayPort and Embedded DisplayPort Tuning Guide

Ethernet Compliance Test Guide

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