PCIe Compliance Testing Reference
PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide DA-11040-001_v0.7 | 16
gear can be connected to PCB probe points with best integrity. In place of breakout boards
customers may use other methods, for example using solder tips for probes.
Customers are required to provide their own solution.
Breakout Boards
Breakout board connections described here are for the NVIDIA proprietary solution. The
following section describes how to connect the breakout board as a reference example:
The breakout board has four solder tips to connect to the PCB opposite to SMA:
P+,
P+GND,
N-,
N-GND.
There are two SMA connectors, opposite to tips, to connect to the scope differential probes.
SMA+
SMA-
To connect the breakout board to the desired solder pad on a PCB, an AWG38 (0.04'' inch) wire
may be used for soldering the breakout board tip pads to the + PAD and its closest GND and to
the PAD. This is used for PCIe lane, and REFCLK measurement. Keep the wires as short as
possible. The shorter the length of the wires used, the better. Ensure that both P and N wires
are similar in length to avoid skew.
Use hot melt adhesive for strain relief and fastening the breakout board onto the PCB. This is
important to avoid strain or movement on the soldered wire when probing. Choose the hot
melt adhesive according to the ambient temperature that the DUT is going to be subjected to.
Higher temperature use case will need a high heat resistance glue to be used.
Alternatively, when using solder tips for 50 Ω (differential) probes, follow the same procedure.
REFCLK Measurement and Characterization
Refer to the
Jetson AGX Orin Design Guide
for recommendations and information regarding
the use of REFCLK and use of spread NVIDIA Spectrum
™
clocking (SSC).
For PCIe controllers acting as and end point (EP), Separate Reference Clocks with No SSC
(SRNS) is recommended. Correct PCIe controller configuration is automatically guaranteed
when loading the OS (configured for this platform with DUT) when booting. When using Sigtest
and Clock Jitter tools, take SRNS or SRIS requirements into consideration.
Gen3 Sigtest post processing with SSC switched on is not supported yet and the tool cannot
process it. Consider the use of PATCH-B (see Table 5) to disable SSC when needed.
The Tx compliance test using PCISIG software Sigtest provides a pass or fail criterion with post
processing including REFCLK trace files. In case the mask fails, it may be hard to determine
the root cause. Before running Tx compliance testing it may be useful to characterize REFCLK
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