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3.2.1 Over Voltage and Under Voltage Protection Circuit

The voltage protection circuit on the EVM protects the board from overvoltage, under voltage and transient

voltage input cases. The safe operation input voltage range is 6 V to 28 V. A fault indication and power good

LEDs are provided to indicate the power status.

Table 3-2. Power LED Status

LED ON Status OFF Status

LD2 Board Power on Board Power off

LD3 Input voltage is >28 V or <6 V Input voltage is within the limit

Figure 3-3. Power ON/Fault LEDs

EVM User Setup/Configuration www.ti.com

14 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022

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Table of Contents1
Introduction4
Key Features4
Thermal Compliance5
Figure 1-1. Thermal Caution5
REACH Compliance6
EMC, EMI, and ESD Compliance6
J721E EVM Overview6
Figure 2-1. J721E EVM Board6
Table 1-1. REACH Compliance6
Figure 2-2. System Architecture Interface7
J721E EVM Board Identification8
Figure 2-3. J721E EVM Board Identification (SOM, CPB, QP Ethernet)8
J721E SOM Component Identification9
Figure 2-4. J721E SOM Component Identification9
Jacinto7 Common Processor Components Identification10
Figure 2-5. Jacinto7 Common Processor Component Identification10
Quad Ethernet Components Identification11
Figure 2-6. Quad Ethernet Component Identification11
EVM User Setup/Configuration12
Power Requirements12
Figure 3-1. Connector Used for Power Input12
Table 3-1. Recommended External Power Supply12
Power on Switch and Power Leds13
Figure 3-2. Power ON/OFF Switch13
Figure 3-3. Power On/Fault Leds14
Table 3-2. Power LED Status14
Figure 3-4. Power Status Leds15
Table 3-3. Power Leds15
Table 3-4. Power Test Points16
EVM Reset/Interrupt Push Buttons17
Figure 3-5. EVM Push Buttons17
Table 3-5. EVM Push Buttons17
EVM DIP Switches18
Figure 3-6. EVM Configuration DIP Switch18
Table 3-6. EVM Configuration Switch Function19
Table 3-7. EVM Configuration Switch Function20
Figure 3-7. BOOT Switches Provided on the Processor Card21
Table 3-8. Wakup Boot Mode Switch (SW9)21
Table 3-9. Main Boot Mode Switch (SW8)21
EVM UART/COM Port Mapping22
Table 3-10. UART Port Mapping22
JTAG Emulation23
Figure 3-8. JTAG Mux23
Table 3-11. JTAG 1:2 Mux Selection23
Table 3-12. TI 60 Pin Connector (J16) Pinout24
Table 3-13. Cti20 Pin Connector (J1-Refer PROC081E2 SCH) Pinout25
Table 3-14. TI14 Pin Connector (J2-Refer PROC081E2 SCH) Pinout25
J721E EVM Hardware Architecture26
J721E EVM Hardware Top Level Diagram26
Figure 4-1. J721E EVM Functional Block Diagram26
Figure 4-2. Quad Port Ethernet Expansion Functional Block Diagram27
J721E EVM Interface Mapping28
Table 4-1. J721E EVM Interface Mapping28
I2C Address Mapping29
Table 4-2. J721E EVM I2C Table29
GPIO Mapping30
Table 4-3. J721E Soc - GPIO Mapping Table30
Power Supply31
Figure 4-3. J721E SOM Power Distribution Block Diagram31
Figure 4-4. Power on Sequencing32
Figure 4-5. Voltage Supervisor Circuit33
Figure 4-6. LPDDR4 IO Voltage Selection Circuit34
Table 4-4. DDR I/O Voltage Selection34
Table 4-5. J721E Soc S2R Logic Flow35
Table 4-6. J721E Soc S2R Logic Flow35
Table 4-7. INA Devices I2C Slave Address36
Table 4-8. External Power Monitor Header Pinouts37
Reset38
Figure 4-7. EVM Reset Architecture38
Clock39
Figure 4-8. EVM Clock Architecture39
Figure 4-9. J721E Soc Primary Clock40
Table 4-9. Processor's Secondary/Serdes Ref Clock41
Table 4-10. EVM Peripheral Ref Clock41
Memory Interfaces42
Figure 4-10. J721E Som LPDDR442
Figure 4-11. J721E Som OSPI and Hyper Flash43
Figure 4-12. UFS Memory Block Diagram44
Figure 4-13. Emmc Memory Block Diagram45
Figure 4-14. Micro-SD Card Block Diagram46
Table 4-11. Board ID Memory Header Information47
MCU Ethernet Interface48
Figure 4-15. MCU Gigabit Ethernet Block48
Figure 4-16. MCU Ethernet PHY Settings49
QSGMII Ethernet Interface50
Table 4-12. Clock Source Selection50
Figure 4-17. Quad-SGMII Board I2C51
Pcie Interface52
Figure 4-18. QSGMII Ethernet PHY Settings52
Figure 4-19. Pcie Interface for SERDES053
Figure 4-20. Pcie SMBUS Block Diagram53
Figure 4-21. 1L-Pcie Root Complex/Endpoint Selection Circuit54
Table 4-13. Reference Clock Selection for Pcie Host Operation54
Table 4-14. Reference Clock Selection for Pcie Endpoint Operation54
Figure 4-22. USB2.0 Header Connection55
Table 4-15. Resistors for Selecting Pcie Card Host or Device55
Figure 4-23. Pcie Interface for SERDES156
Figure 4-24. 2L-Pcie Root Complex/Endpoint Selection Circuit56
Table 4-16. Reference Clock Selection for Pcie Host Operation57
Table 4-17. Reference Clock Selection for Pcie Endpoint Operation57
Table 4-18. Resistors for Selecting Pcie Card Host or Device Operation57
USB Interface58
Figure 4-25. Pcie Interface for SERDES258
Figure 4-26. USB3.1 Type C Interface59
Figure 4-27. Type C Power Delivery Current Settings59
Figure 4-28. USB Hub Reference Clock Circuit60
Figure 4-29. USB Hub Settings Circuit60
Figure 4-30. USB1 ID Setting for HUB60
CAN Interface61
Figure 4-31. MCU CAN0 Interface61
Figure 4-32. CAN Wake Push Button62
Figure 4-33. CAN Header Connections to Db9/Test Instrument63
FPD Interface (Audio Deserializer)64
Figure 4-34. FPD-Link UB926 ID Setting Circuit64
Figure 4-35. FPD-Link UB926 Mode Selection Circuit64
FPD Panel Interface (DSI Video Serializer)65
Figure 4-36. FPD-Link UB941A Device Settings Circuit65
Table 4-19. FPD Audio Deserializer HSD Connector Pinout65
Table 4-20. DSI to FPD Serializer HSD Connector Pinout65
Display Serial Interface (DSI) FPC66
Audio Interface66
Table 4-21. MCASP/TRACE - 1:3 MUX: Truth Table66
Table 4-22. Config Table66
Figure 4-37. Audio Port Interface Assignment67
Display Port Interface68
MLB Interface68
Figure 4-38. Display Port Block Diagram68
Figure 4-39. MLB Interface Connector69
Table 4-23. MLB Header Pinout69
I3C Interface70
ADC Interface70
Figure 4-40. ADC Interface Connector70
Table 4-24. MCU I3C Header J33 Pinout70
Table 4-25. MAIN I3C Header J3270
RTC Interface71
Figure 4-41. RTC Block Diagram71
Table 4-26. ADC Header J2371
Apple Authentication Header72
Figure 4-42. Apple Authentication Block Diagram72
Table 4-27. APPLE AUTH Header J972
EVM Expansion Connectors73
Figure 4-43. Expansion Board Interface Connectors73
Table 4-28. APPLE AUTH Footprint U108 Pinout73
Table 4-29. EVM Expansion Connector J4674
Table 4-30. EVM Expansion Connector J5176
ENET Expansion Connector77
Table 4-31. ENET Expansion Board Power Test Points77
Figure 4-44. CDCI I2C Isolation Circuit78
Table 4-32. ENET Expansion Connector J10 Pinout79
Table 4-33. CSI Expansion Connector J52 Pinout82
Table 4-34. CSI Expansion Connector J48 Pinout82

Brand	Texas Instruments
Model	J721E
Category	Motherboard
Language	English

Texas Instruments J721E User Manual

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