4.8.2 OSPI Interface
The J721E SOM has 512 Mbit OSPI memory device of part number MT35XU512ABA1G12-0SIT connected to
OSPI0 interface of J721E processor. The OSPI interface supports single and double data rates with memory
speed up to 166 MHz SDR and 200 MHz DDR.
The SOM board also supports an option to include Hyper Flash + Hyper RAM Mfr. Part# S71KS512SC0, which
is a 512 Mb flash + 64 Mb DRAM. 12-bit Active mux TS3DDR3812RUAR is provided to select either OSPI
or HBMC interface. The selection of OSPI and hyper flash will be done by using a DIP (SW3) switch that is
populated on the CP board. For more information, see Section 3.4.1.
Figure 4-11. J721E SoM OSPI and Hyper Flash
www.ti.com J721E EVM Hardware Architecture
SPRUIS4D – MAY 2020 – REVISED MARCH 2022
Submit Document Feedback
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) 43
Copyright © 2022 Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
