4.5.3.1 J721E SoC S2R Logic Flow Diagram
The EVM supports a low power state referred to as Suspend-to-RAM (or S2R). This state allows the processor
(or optionally the entire system) to be powered off while the LPDDR4 memory is maintained in self refresh mode.
The power state is managed through the PMIC(s). Table 4-5 shows the steps required to enter the S2R state:
Table 4-5. J721E SoC S2R Logic Flow
Leo PMIC Transition From Active Mode to S2R Mode
Action Address Bits Data Register/Bit Names
Unmask GPIO10_RISE-MASK on LeoA (I2CID: 0x48) 0x51 [4] 0x0 GPIO10_RISE_MASK
Read and write to clear the WKUP1 interrupt 0x63 [1] 0x1 GPIO10_INT
Reconfigure GPIO4 of LeoA to LP_WKUP1 0x34 [7:0] 0xC8 GPIO4_CONFIG
Read and write to clear the LP_WKUP1 interrupt 0x64 [4] 0x1 GPIO_INT
Set nSLEEP2b and nSLEEP1b to '00' to go to S2R state 0x86 [1:0] 0x0 NSLEEP2b, NSLEEP1b
Read and write to clear the ENABLE_INT interrupt 0x65 [1] 0x1 ENABLE_INT
The EVM can be woke from the low power state by pressing the CAN_WAKEn button (SW12).
4.5.3.2 J721E SoC MCU Only Operation
Table 4-6. J721E SoC S2R Logic Flow
Leo PMIC Transition From Active Mode to S2R Mode
Action Address Bits Data Register/Bit Names
Unmask GPIO10_RISE-MASK on LeoA (I2CID: 0x48) 0x51 [4] 0x0 GPIO10_RISE_MASK
Read and write to clear the WKUP1 interrupt 0x63 [1] 0x1 GPIO10_INT
Reconfigure GPIO4 of LeoA to LP_WKUP1 0x34 [7:0] 0xC8 GPIO4_CONFIG
Read and write to clear the LP_WKUP1 interrupt 0x64 [4] 0x1 GPIO_INT
Set nSLEEP2b and nSLEEP1b to '10' to go to
MCU_ONLY state
0x86 [1:0] 0x2 NSLEEP2b, NSLEEP1b
Read and write to clear the ENABLE_INT interrupt 0x65 [1] 0x1 ENABLE_INT
The EVM can be woke from the low power state by the MCU issuing commands to the PMIC through I2C.
www.ti.com J721E EVM Hardware Architecture
SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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