4.20 I3C Interface
Common Processor board supports two I3C headers to validate the J721E SoC’s MCU and MAIN domain
I3C interfaces. Out of Two I3C headers, only the MCU I3C header J33 is populated on J721E EVM and the
MAIN I3C header J32 is not populated by default. MCU_I3C0_SDA is pulled through 1K Resistor by signal
MCU_I3C0_SDAPULLEN from SoC.
MAIN_I3C0_SCL and MAIN_I3C0_SDA are terminated to the I3C header using 2:1 de-muxer IC U46 on
Common Processor board. The signal path is disconnected by default using resistors R192 and R193.
The mux selection is controlled by I2C GPIO Expander2 (I2C ADD# 0x22, I2C0) Port16.
Table 4-24 and Table 4-25 lists the I3C Header pinouts.
Table 4-24. MCU I3C Header J33 Pinout
Pin No Signal
1 DGND
2 MCU_I3C0_SDA
3 MCU_I3C0_SCL
Table 4-25. MAIN I3C Header J32 Pinout
Pin No Signal
1 DGND
2 MCU_I3C0_SDA
3 MCU_I3C0_SCL
4.21 ADC Interface
MCU ADC0 port of J721E SoC is interfaced to 2x10 header Mfr. Part# TSW-110-07-S-D on Common Processor
board. The ADC inputs MCU_ADC0_AIN[7:0] and external Trigger input MCU_ADC_EXT_TRIGGER0 is
connected to J721E SoC through SoM board. MCU_ADC0_REF_P and MCU_ADC0_REF_N are not routed
to J721E SoC as these signals are tied internally in SoC package.
Note
MCU ADC1 port of J721E SoC is supported on EVM application board (GESI).
Figure 4-40. ADC Interface Connector
J721E EVM Hardware Architecture www.ti.com
70 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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