SARA-R5 series - System integration manual
UBX-19041356 - R04 System description Page 11 of 118
C1-Public
1.3 Pin-out
Table 3 lists the pin-out of the SARA-R5 series modules, with pins grouped by function.
VCC supply circuit affects the RF performance and compliance
of the device integrating the module with applicable required
certification schemes.
See section 1.5.1 for functional description / requirements.
See section 2.2.1 for external circuit design-in.
1, 3, 5, 14,
20-22, 30,
32, 43,
50, 54,
55, 57-61,
63-96
GND pins are internally connected to each other.
External ground connection affects the RF and thermal
performance of the device.
See section 1.5.1for functional description.
See section 2.2.1 for external circuit design-in.
Generic digital
interfaces supply
output
V_INT = 1.8 V (typical) generated by internal regulator when the
module is switched on, outside the low power PSM deep-sleep
mode.
See section 1.5.2 for functional description.
See section 2.2.2 for external circuit design-in.
Provide test point for diagnostic purposes.
Internal active pull-up.
See sections 1.6.1, 1.6.2 for functional description.
See section 2.3.1 for external circuit design-in.
Provide test point for diagnostic purposes.
Internal active pull-up.
See section 1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
Provide test point for diagnostic purposes.
50 nominal characteristic impedance.
Antenna circuit affects the RF performance and application
device compliance with required certification schemes.
See section 1.7.1 for functional description / requirements.
See section 2.4.2 for external circuit design-in.
50 nominal characteristic impedance.
See section 1.7.2 for functional description / requirements.
See section 2.4.3 for external circuit design-in.
ADC for antenna presence detection function.
See section 1.7.3 for functional description.
See section 2.4.5 for external circuit design-in.
VSIM = 1.8 V / 3 V output as per the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Data input/output for 1.8 V / 3 V SIM.
Internal pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Clock output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Reset output for 1.8 V / 3 V SIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Not supported by SARA-R500S and SARA-R510S modules