Xerox 560 Reference Manual

single-instruction interrupt location, the instruction in the
interrupt location is executed and then instruction execution
proceeds with the next instruction in sequence after the
WAIT instruction. When the basic processor execution mode
is
changed from RUN mode to IDLE mode and back to RUN
while the basic processor is waiting, instruction execution
proceeds with the next instruction in sequence after the
WAIT instruction.
Affected: PC
If WAIT is indirectly addressed and the indirect reference
address is nonexistent, the nonallowed operation trap to
location X
'
40
'
will not occur. The effective virtual address
of the WAIT instruction, however, is not used as a memory
reference (thus does not affect the norma I operation of the
instruction).
RD READ DIRECT
(Word index alignment, privileged)
The basic processor is capable of directly communicating
with
other elements of the system, as well as performing
internal control operations, by means of the READ DIRECT /
WRITE DIRECT (RD/'ND) lines. The RD;WD lines consist of
16 address lines, 32 data lines, two condition code lines,
and various control I ines that are connected to various basic
processor circuits and to special system equipment.
READ DIRECT causes bits 16 through 31 of the effective
virtual address to be presented to other elements ofthe sys-
tem on the RD/'ND address lines. Bits 16-31 of the effective
virtual address identify a specific elementof the system that
is expected to return information (two condition code bits
plus a maximum
of 32 data bits) to the basic processor. The
significance and number of data bits returned depend on the
selected element. If the R field of RD is nonzero, up to
32 bits of the returned data are loaded into general regis-
ter R; however, if the R field of RD is 0, the returned data
is ignored and general register a is not changed. Bits CC3
and CC4 of the condition code are set by the addressed
element, regardless of the value of the R field.
Bits 16-19 of the effective virtual address of RD determine
the mode of the RD instruction, as follows:
Bit
Position
16 17 18 19
Mode
a a a a Interna I basi c processor control.
o a a
Interrupt control.
a a
a Xerox testers.
120 Control Instructions
16 17 18 19
a a
: ]
Unass igned.
Special systems control (for customer use
with
specially designed equipment).
If bits 16-19 select mode 2 through mode F, CC 1 and CC2
are set to zero and CC3 and CC4 are set according to the
state of the two condition code lines from the external
device.
READ DIRECT. INTERNAL BASIC PROCESSOR
CONTROL (MODE 0)
In this mode, the basic processor is able to read the sense
switches, the basic processor address, and the interrupt in-
hibit bits of the PSWs as follows:
READ SENSE SWITCHES
The following configuration of RD can be used to read the
four SENSE switches in the System Control Processor:
If a particular SENSE switch is set, the corresponding bit of
the condition code is set to 1; if a SENSE switch is zero,
the corresponding bit of the condition code is set to a (see
"Read Sense Switches" in Chapter 5).
In this case, only the condition code is affected.
READ BASIC PROCESSOR
The following RD configuration is used to read the basic
processor's address:
If the R field is nonzero, the cluster number in which the
basic processor resides is obtained from the associated pro-
cessor interface and loaded into register R bits 21-23. All
other bits in the register are cleared to zero.
Affected: (R)
Cluster Address - R
21
-
23
0- R
O
-
20
and R
24
-
31

Xerox 560 Specifications

General

Brand	Xerox
Model	560
Category	Printer
Language	English