Xerox 560 Reference Manual

TRAP MASKS
The programmer may mask the four trap conditions described
below in the program status words (PSWs) or the stack pointer
doubleword, as appropriate; other traps cannot be masked.
1. The push-down stack I imit trap is masked within the
stack pointer doubleword for each individual stack.
2. The fixed-point overflow trap is masked in bit posi-
tion 11 (AM) of the PSWs. If this bit position contains
a zero, the trap is allowed to occur; if bit 11 contains
a zero, the trap is not allowed to occur. AM can be
masked by operator intervention, or by execution of
the XPSD, PSS, PLS, or LPSD privileged instructions.
3. The floating-point significance check trap is masked
by a
combination of the floating significance (FS),
floating zero (FZ), and floating normalize (FN) mode
control bits in
the PSWs (see IIFloating-Point Arithme-
tic Fault Trapll, later in this chapter). FS, FZ, and
FN can be set or cleared by the execution of any of
the following instructions:
LOAD CONDITIONS AND FLOATING CON-
TROL (LCF)
LOAD CONDITIONS AND FLOATING CON-
TROL IMMEDIATE (LCFI)
EXCHANGE
PROGRAM STATUS WORDS (XPSD)
LOAD PROGRAM
STATUS WORDS (LPSD)
PUSH STATUS (PSS)
PULL STATUS (PLS)
4. The decimal arithmetic fault trap is masked by bit po-
sition 10 (DM) of the PSWs. If DM contains a one,
the trap is allowed; if DM contains a zero, the trap is
not
allowed. DM can be masked by execution of
the X PSD, PSS, PLS, or LPSD privi leged instruction.
with the condition code bits (CC1-CC4) of the new PSWs
when loading CC1-CC4. See also IIInstruction Exception
Trapll later in this chapter for more information on the trap
condition code.
NONALLOWED OPERATION TRAP
The attempt to perform a nonallowed operation always
causes the basic processor to abort the instruction being ex-
ecuted when the nonallowed operation is detected and to
immediately execute the XPSD or PSS instruction in trap lo-
cation X
1
40
1
• A nonallowed operation cannot be masked.
NONEXISTENT INSTRUCTION
Any instruction that is not standard is defined as nonexist-
ent. This includes immediate operand instructions that
specify indirect addressing (a one in bit 0 of the instruction).
If a nonexistent instruction is detected, the basic processor
traps to
location X 140
1
when the nonexistent instruction is
decoded. No general registers or memory locations are
changed; the PSWs point to the instruction trapped. With
respect to the condition code and instruction address fields
of the program status words, the operation of the XPSD or
PSS in location X 140
1
is as follows:
1. Store the current PSWs. The condition codes stored are
those that existed at the end of the last instruction
prior to the nonexistent instruction.
2. Store the 16 general registers of the current register
block if instruction in trap location is a PSS.
3. Load the new PSWs.
4. Modify the new PSWs.
a. Set CCl to one. The other condition code bits
TRAP CONDITION CODE remain unchanged from the values loaded from
For
the push-down stack limit trap, fixed-point overflow
trap, floating-point fault trap, and decimal fault trap, the
normal condition code register (CC 1-CC4) is loaded with
more detai led information about the trap condition just
before the trap occurs. These condition codes are saved as
part of the old program status words when the XPSD or PSS
instruction is executed in response to the trap.
For the nona I lowed operation trap, watchdog timer runout
trap, hardware error trap, instruction exception trap, and
CALL trap, a special register (trap condition codes TCC1-
TCC4) is loaded just before the trap occurs. When the
X PSD or PSS instruction is executed in response to the trap,
this register is added to the new program address if bit 9
(MM)
contains a one; TCC 1- TCC4 are also logically ORed
memory.
b. If bit position 9 (AI) of the X PSD or PSS instruc-
tion contains a one, the program counter is incre-
men ted by eight. If AI contains a zero, the
program counter remains unchanged from the value
loaded from memory.
NONEXISTENT MEMORY ADDRESS
Any attempt to access a nonexistent memory address causes
a trap
to location X
l
40
1
at the time of the request for mem-
ory
service. A nonexistent memory address condition is
detected when an actual address is presented to the memory
T rap System
39

Xerox 560 Specifications

General

Brand	Xerox
Model	560
Category	Printer
Language	English