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Xerox 560 Reference Manual

Xerox 560
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READ
DIRECT
(MODE
9)
READ
CONFIGURATION
CONTROL
PANEL
The mode 9 instruction
reads
the
state
of
the
Configuration
Control
Panel for
the
addressed
cluster
or
unit.
Physical
addresses
are
assigned
at
the
time
of
system
configuration.
The
returned
status
to
Register R is shown in
Tables
11
and
12.
WD
WRITE
DIRECT
0/Vord
index
alignment,
privileged)
WRITE
DIRECT
causes bits 16-31
of
the
effective
virtual
ad-
dress
to
be
presented
to
other
elements
of
the
system on
the
RD;WD address lines (see
READ
DIRECT). Bits 16-31
of
the
effective
virtual
address
identify
a
specific
element
of
the
system
that
is
to
receive
control information from
the
basic
processor. If
the
R
field
of
WD
is
nonzero,
the
32-bit
con-
tents
of
register
R
are
transmitted
to
the
specified
element
on
the
RD;WD
data
I
ines.
If
the
R
field
of
WD
is
0,32
O's
are
transmitted
to
the
specified
element
(instead
of
the
con-
tents
of
register
0). The
specified
element
may return
information
to
set
the
condition
code.
Bits
16-19
of
the
effective
virtual
address
determine
the
mode
of
the
WD
instruction,
as follows:
16 17
18
19
Mode
o 0 0 0 Interne! basic processor centro!.
000
Interrupt
control.
000
Xerox
testers.
o 0
Unassigned.
Special
systems control (for customer use
••
I •
'I
••
• • • \
wlfn speCIallY
aeslgnea
equlpmenr).
If
bits
16-19
select
mode 2 through mode F,
CC
1
and
CC2
are
set
to
zero
and
CC3
and
CC4
are
set
according
to
the
state
of
the
two
condition
code
I ines from
the
externa
I
device.
122 Control Instructions
WRITE
DIRECT,
INTERNAL
BASIC
PROCESSOR
CONTROL
(MODE
0)
LOAD SENSE SWITCHES
The fol lowing
configuration
of
WD
can
be used
to
load
the
sense switches
in
the
System Control Processor:
If
the
R
field
is
nonzero,
bits 0 through 3
of
Register R
will
be
loaded into sense switches 1 through 4
in
the
System
Control Processor.
If
the
R
field
is
zero,
sense
switches
will
be
reset
to
zeros.
(See
the
section
"System Control
Panel"
in
Chapter
5.)
SET
INTERRUPT
INHIBITS
The following
configuration
of
WD
can
be used
to
set
the
interrupt
inhibits
(bit
positions
37-39
of
the
PSWs):
A
logical
inclusive
OR
is performed
between
bits
29-31
of
the
effective
virtual
address
and
bits
37-39
of
the
PSWs.
If
any
(or
all)
of
bits
29-31
of
the
effective
virtual
address
are
l's,
the
corresponding
inhibit
bits in
the
PSWs
are
set
to
l's;
the
current
state
of
an
inhibit
bit
is
not
affected
if a
corresponding
bit
position
of
the
effective
virtual
address
contains
a
O.
Note
that
a copy
of
the
Interrupt Inhibits is
retained
in
the
Interrupt Status Register in
the
Processor
Interface
associated
with
each
basic
processor.
RESET
INTERRUPT
INHIBITS
The
following
configuration
of
WD
can
be used to
reset
the
interrupt
inhibits:
If
any
(or
al
I)
of
bits
29-31
of
the
effective
virtual
address
are
l's,
the
corresponding
inhibit
bits in
the
PSWs
are
reset
to
0'5,
the
current
state
of
an
inhibit
bii is
not
affected
if
a corresponding
bit
position
of
the
effective
virtual
address
contains
a
O.
Note
that
a
copy
of
the
Interrupt Inhibits
is
retained
in
the
Interrupt
Status Register in
the
Processor
Interface
associated
with
each
basic
processor.

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Xerox 560 Specifications

General IconGeneral
BrandXerox
Model560
CategoryPrinter
LanguageEnglish

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