Term
FZ
IA
II
L
MA
MM
MS
PSWs
R
RA
Ref.
Add.
Meaning
Floating zero mode
control-bit
position 6
of
the
PSWs.
If set (=1), basic processor
traps to location X·44· when
either
charac-
teristic underflow or zero result occurs for
a
floating-point
multiplication or division;
if not
set,
characteristic
underflow
and
zero
resu
It
are
treated
as normal conditions.
Instruction
register-internal
basic processor
register
that
holds instructions obtained from
memorywhile
they
are being
decoded.
Instruction
address-
17~bit
value
that
defines
virtual address
of
instruction immediately
prior
to
the
time
that
it
is
executed.
I/o interrupt group inhibit -
bit
position 38
of
the
PSWs.
If set (=1), all interrupt levels
within this group
are
inhibited.
Numeric
value
of bits 8-11 of decimal
in-
struction word (value
of.
0
is
16
bytes).
Mode
altered
- bit position
61
of
PSWs.
This
bit
is
set
(=
1)
during master-protected
mode of operation and during real
extended
type
of addressing.
Memory map mode
control-position
9 of
PSWs.
When set (=1),
the
memory map
is
in
effect.
Master/slave mode
control-bit
position 8
of
PSWs.
When set (=1), basic processor
is
in
slave
mode; when not
set,
basic
proces-
sor may
be
in
master
or
master-protected
mode as determined by
bit
40.
Program status words -
collection
of
sepa-
rate registers
and
flip-flops
treated
as
an
internal basi c processor register to store and
display criti cal control information.
General
register address
value-4-bit
con-
tents of
bit
positions 8-11
(R
field) of
instruction word, also expressedsymbolically
as
(I)8-11.
In
instruction descri ptions,
regis-
ter
R
is
general register (of current register
block)
that
corresponds
to
R
fi
eld address
value.
Register
altered
- bit position 60 of
PSWs.
When
trap
occurs, this bit set
(=
1)
when
gen-
eral register or memory location
altered
in
execution of instruction causing
the
trap.
Reference address - contents of bit
posi-
tions 15-31 of instruction word, a
17-bit
field
capable
of
directly
addressing
any
Term
Ref.
Add.
(cont .)
RP
Ru1
SA
SBS
SE
SPD
TCC
TS
TSA
TW
Meaning
general register in current register block
(by using a
value
in range 0-15) or
any
word
in
main memory in address range
16
through
131,071.
This address value
is
initial
ad-
dress
value
for
any
subsequent address
com-
putations, memory mapping, or both
computation and mapping.
Register pointer -
bit
positions 58 and
59
of
PSWs;
these bits
select
one of four possible
register blocks.
Odd
register address
value
- register
Ru1
is
general register pointed to by
value
obtained
by
logically
ORing 0001 into address for
register
R.
Thus, if R field of instruction
contains even
value,
Ru
1 = R + 1
and
if R
field contains odd
value,
Ru1
=
R.
Source address - in
byte-string
instructions,
contents of speci
fi
ed R reg ister.
Source byte
string-operand
specified
by
byte string instruction.
Sign extension - some instructions
operate
on
two operands of different lengths;
they
are
made equal in length by extending
sign of shorter operand by required num-
ber
of
bit
positions. For positive operands,
result of sign extension
is
high-order
O·s
prefixed
TO
Tne
operano;
Tor
negative
op-
erands,
high-order
l·s
are
prefixed
to
op-
erand.
Sign extension process
is
performed
after
operand accessed from memory and
before operation
called
for by instruction
code
is
performed.
Stack pointer doubleword - contains
the
context
(TSA,
space
count, word
count,
and
TS,
TW
inhibit bits)
of
the
push-down
instructions.
Trap condition
code
-
4-bit
value
(bit
positions
labeled
TCC1, TCC2, TCC3,
and TCC4), established as part of
trap
operations.
Trap-on-space
inhibit bit - conditions push-
down
stack
limit
trap
for impending overflow
or underflow
of
space
count.
Top-of-stack
address - pointer
that
points
to highest-numbered address of operand
stack
in push-down instructions.
Trap-on-word inhibit
bit-conditions
push-
down
stack
limit trap for impending
over-
flow or underflow of word
count.
Appendix B 193
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