4.
INPUT/OUTPUT OPERA TIO NS
142
AGURES
External DIO
Interface
142
1.
A Xerox 560
Computer
System
9
Multiplexor
Input/Output
Processor (MIOP)
Devi
ce
Controllers
142
2.
The Basic Processor 10
Rotating Memory Processor (RMP)
143
Input/Output
Processor
(lOP)
Fundamentals
__
143
3.
Information Boundaries 13
Command List
143
Operational
IOCD
143
4.
Main
Memory
15
Control
IOCD
146
I/o
Operation
Phases 148
5.
Addressing Logic
18
Preparation
Phase
148
Initiation
Phase
148
6.
Index
Displacement
Alignment
(Real
and
Fetching
Phase
148
Virtual Addressing Modes)
21
Execution
Phase
149
Termination
Phase
151
7.
Generation
of
Actual
Addresses
Indirect,
Virtual Addressing
22
5.
OPERATIONAL
CONTROL
152
8.
Index
Displacement
Alignment
(Real-
Extended Addressing)
23
Externa I Control Subsystem
152
Central
ized
System
Control
152
9.
Generation
of
Effective
Virtual Address
Control
Console
Devices
152
(Indirect
Real-Extended
Addressing)
24
Control
Commands 153
Operator
Control Commands
153
10.
Operational
States
of
an
Interrupt
Level
31
Diagnosti c Control Commands 156
Maintenance
Control Commands 158
1l.
Interrupt
Priority
Chain
34
System Control Panel
161
Operating
Procedures
and
Information
___
164
12.
Typical
28-Word
Portion
of
Memory
Stack
for
PSS
and
P
LS
102
6.
SYSTEM
CONFIGURATION
CONTROL
167
13.
Formats
of
I/o
Instructions 128
Configuration
Control Panel (CCP)
167
14.
Bootstrap Loader
155
15.
APPENDIXES
System Control Panel 162
16.
Chassis Physical
Configuration
168
A.
REFERENC
E
TABLES
173
17.
Sample
Rows
of
CCP
Switches
168
Standard
Symbols
and
Codes
173
Standard
Character
Sets
173
Control
Codes
173
Special
Code
Properties
173
Standard
8-Bit
Computer
Codes
(EBCDIC)
___
174
Standard
7-Bit
Communication
Codes
TABLES
(ANSCII) 174
Standard
Symbol-Code
Correspondences
175
l.
Basic Processor
Operating
Modes
and
Hexadecimal
Arithmetic
179 Address i ng
Cases
25
Addition
Table
179
Multiplication
Table
179
2.
Interrupt
Locations
33
Table
of
Powers
of
SixteenlO
180
Table
of
Powers
of
Ten16
180
3.
Summary
of
Trap Locations
37
Hexadecimal-Decimal
Integer
Conversion
Table
181
4.
TCC
Setting
for Instruction Exception
Hexadecimal-Decimal
Fraction
Conversion
Trap X
'
4D
'
44
Table
187
Table
of
Powers
of
Two
191
5.
Registers
Changed
at
Time
of
a Trap Due to
Mathematica
I Constants
191
an
Operand
Access 45
B.
GLOSSARY OF SYMBOLIC
TERMS
192
6.
ANALYZE
Table
for
Operation
Codes
57
C.
FAULT
STATUS
REGISTERS
195
7.
Floating-Point
Number Representation
76
iv
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