Xilinx ML605 Hardware User's Guide

26 www.xilinx.com ML605 Hardware User Guide
UG534 (v1.9) February 26, 2019
Chapter 1: ML605 Evaluation Board
FPGA Design Considerations for the Configuration Flash
After FPGA configuration, the FPGA design can disable the configuration flash or access
the configuration flash to read/write code or data.
When the FPGA design does not use the configuration flash, the FPGA design must drive
the FPGA FCS_B pin High in order to disable the configuration flash and put the flash into
a quiescent, low-power state. Otherwise, the Platform Flash XL, in particular, can continue
to drive its array data onto the data bus causing unnecessary switching noise and power
consumption.
For FPGA designs that access the flash for reading/writing stored code or data, connect
the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash
through the pins defined in Table 1-5.
The Platform Flash XL defaults to a synchronous read mode. Typically, the Platform Flash
XL requires an initialization procedure to put the Platform Flash XL into the common,
asynchronous read mode before accessing stored code or data. To put the Platform Flash
XL into asynchronous read mode, apply the Set Configuration Register command
sequence. See the Platform Flash XL High-Density Configuration and Storage Device Data Sheet
(DS617) for details on the Set Configuration Register command. [Ref 17]
See the Numonyx StrataFlash Embedded Memory Data Sheet. [Ref 27]
Visit the Xilinx Platform
Studio and the Embedded Development Kit product page and
click the Resources tab for more information.
Also, see the Platform Flash XL High-Density Configuration and Storage Device Data Sheet
(DS617) [Ref 17] and the Virtex-6 Configuration User Guide (UG360) [Ref 10].
Send Feedback

Xilinx ML605 Specifications

General

Brand	Xilinx
Model	ML605
Category	Motherboard
Language	English