Xilinx SP605 User Manual

SP605 Hardware User Guide www.xilinx.com 65
UG526 (v1.9) February 14, 2019
Appendix C
Xilinx Design Constraints
Overview
The Xilinx Design Constraints (XDC) file template provides for designs targeting the SP605
evaluation board. Net names in the constraints correlate with net names on the latest SP605
evaluation board schematic. Identify the appropriate pins and replace the net names with
net names in the user RTL.
See the
Constraints Guide (UG625) [Ref 12] for more information.
Note:
The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V
(nonadjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are
compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
Note: The latest version of the Xilinx constraint file can be found on the Spartan-6 FPGA SP605
Evaluation Kit website.

Xilinx SP605 Specifications

General

Brand	Xilinx
Model	SP605
Category	Motherboard
Language	English