Xilinx ZCU104 User Manual

ZCU104 Board User Guide 46
UG1267 (v1.1) October 9, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
GEM3 Ethernet (MIO 64-77)
The PS-side Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet
interface (see Figure 3-9), which connects to a TI DP83867IRPAP Ethernet RGMII PHY U98
routed to an RJ45 Ethernet connector. The RGMII Ethernet PHY is boot strapped to PHY
address 5'b01100 (0 x0C) and Auto Negotiation is set to Enable. The communication with
the device is described in the DP83867 RGMII PHY data sheet [Ref 16].
10/100/1000 MHz Tri-Speed Ethernet PHY
[Figure 2-1, callout 9]
The ZCU104 board uses the TIDP83867IRPAP Ethernet RGMII PHY [Ref 16] (U98) for
Ethernet communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII
mode only. The PHY connection to a user-provided Ethernet cable is through a Bel Fuse
L829-1J1T-43 RJ-45 connector (P12) with built-in magnetics and LED indicators. The
connections from XCZU7EV MPSoC U1 to the DP83867IRPAP PHY device U98 (bottom of the
board) are listed in Table 3-14.
X-Ref Target - Figure 3-9
Figure 3-9: Ethernet Block Diagram
Table 3-14: DP83867 PHY Connections to XCZU7EV MPSoC
XCZU7EV
(U1) Pin
Net Name
DP83867 PHY U98
Pin # Pin Name
J31 MIO64_ENET_TX_CLK 40 GTX_CLK
J32 MIO65_ENET_TX_D0 38 TX_DO
J34 MIO66_ENET_TX_D1 37 TX_D1
K28 MIO67_ENET_TX_D2 36 TX_D2
K29 MIO68_ENET_TX_D3 35 TX_D3
K30 MIO69_ENET_TX_CTRL 52 TX_EN_TX_CTRL
TI
DP83867IR
GEM
MIO
RGMII
MDIO
RJ45 and
Magnetics
X16527-100818
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Xilinx ZCU104 Specifications

General

Brand	Xilinx
Model	ZCU104
Category	Motherboard
Language	English