IBM BladeCenter PS700 User Manual

Chapter 2. Architecture and technical overview 39
IBM has been innovative to achieve required levels of throughput and bandwidth. Areas of
innovation for the POWER7 processor and POWER7 processor-based systems include (but
are not limited to) the following elements:
򐂰 On-chip L3 cache implemented in embedded dynamic random access memory (eDRAM)
򐂰 Cache hierarchy and component innovation
򐂰 Advances in memory subsystem
򐂰 Advances in off-chip signalling
򐂰 Exploitation of long-term investment in coherence innovation
The superscalar POWER7 processor design also provides a variety of other capabilities:
򐂰 Binary compatibility with the prior generation of POWER processors
򐂰 Support for PowerVM virtualization capabilities, including PowerVM Live Partition Mobility
to and from POWER6 and POWER6+™ processor-based systems
Figure 2-2 shows the POWER7 processor die layout with the major areas identified:
processor cores, L2 cache, L3 cache and chip interconnection, simultaneous multiprocessing
(SMP) links, and memory controllers.
Figure 2-2 POWER7 processor architecture
2.2.1 POWER7 processor overview
The POWER7 processor chip is fabricated with the IBM 45 nm Silicon-On-Insulator (SOI)
technology using copper interconnects, and implements an on-chip L3 cache using eDRAM.
The POWER7 processor chip is 567 mm
2
and is built using 1.2 billion components
(transistors). Eight processor cores are on the chip, each with 12 execution units, 256 KB of
L2 cache, and access to up to 32 MB of shared on-chip L3 cache.
For memory access, the POWER7 processor includes two DDR3 (Double Data Rate 3)
memory controllers, each with four memory channels. To scale effectively, the POWER7
processor uses a combination of local and global SMP links with high coherency bandwidth
and makes use of the IBM dual-scope broadcast coherence protocol.
C1
Core
L2
4MB L3
Memory Controller 1
L2
C1
Core
4MB L3
Memory Controller 0
C1
Core
L2
4MB L3
C1
Core
L2
4MB L3
C1
Core
L2
4MB L3
L2
C1
Core
4MB L3
L2
C1
Core
4MB L3
L2
C1
Core
4MB L3
SMP
GX+ Bridge
Memory buffers Memory buffers

IBM BladeCenter PS700 Specifications

General

Brand	IBM
Model	BladeCenter PS700
Category	Server
Language	English