40 IBM BladeCenter PS700, PS701, and PS702 Technical Overview and Introduction
Table 2-1 summarizes the technology characteristics of the POWER7 processor.
Table 2-1 Summary of POWER7 processor technology
2.2.2 POWER7 processor core
Each POWER7 processor core implements aggressive out-of-order (OoO) instruction
execution to drive high efficiency in the use of available execution paths. The POWER7
processor has an instruction sequence unit that is capable of dispatching up to six
instructions per cycle to a set of queues. Up to eight instructions per cycle can be issued to
the instruction execution units. The POWER7 processor has a set of twelve execution units
as follows:
2 fixed point units
2 load store units
4 double precision floating point units
1 vector unit
1 branch unit
1 condition register unit
1 decimal floating point unit
The caches that are tightly coupled to each POWER7 processor core are as follows:
Instruction cache: 32 KB
Data cache: 32 KB
L2 cache: 256 KB, implemented in fast SRAM
Technology POWER7 processor
Die size 567 mm
2
Fabrication technology 45 nm lithography
Copper interconnect
Silicon-on-Insulator
eDRAM
Components 1.2 billion components (transistors) offering the equivalent
function of 2.7 billion (For further details, see 2.2.6, “On-chip
L3 cache innovation and intelligent cache” on page 43)
Processor cores 8
Max execution threads core/chip 4/32
L2 cache core/chip 256 KB / 2 MB
On-chip L3 cache core/chip 4 MB / 32 MB
DDR3 memory controllers 2
SMP design-point Up to 32 sockets with IBM POWER7 processors
Compatibility With prior generation of POWER processor
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