Name: Keithley 3730
Brand: Keithley
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In this appendix:

Overview ................................................................................. C-1

Status model diagrams ............................................................ C-3

Status function summary ....................................................... C-13

Clearing registers .................................................................. C-13

Startup state .......................................................................... C-14

Programming and reading registers ...................................... C-14

Status byte and service request (SRQ) ................................. C-15

TSP-Link system status ......................................................... C-20

Overview

Each Keithley Instruments Series 3700A provides a number of status registers and queues that are

collectively referred to as the status model. Through manipulation and monitoring of these registers

and queues, you can view and control various instrument events. You can include commands in your

test program that can determine if a service request (SRQ) event has occurred and the cause of the

event.

The heart of the status model is the Status Byte Register. All status model registers and queues flow

into the Status Byte Register.

The entire status model is illustrated in the Status model diagrams.

Status Byte Register

The Status Byte Register receives summary bits from the other status register sets and queues, and

also from itself (which sets the Master Summary Status, or MSS, bit). For details, see Status Byte

Status register set contents

Typically, a status register set contains the following registers:

• Condition (.condition): A read-only register that is constantly updated to reflect the present

operating conditions of the instrument.

• Enable Register (.enable): A read-write register that allows a summary bit to be set when an

enabled event occurs.

• Event Register (.event): A read-only register that sets a bit to 1 when the applicable event

occurs. If the enable register bit for that event is also set, the summary bit of the register will set

to 1.

• Negative Transition Register (NTR) (.ntr): When a bit is set in this read-write register, it

enables a 1 to 0 change in the corresponding bit of the condition register to cause the

corresponding bit in the event register to be set.

Appendix C

Status model

Keithley 3730 Reference Manual

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