Theory of Operation—2230 Service
a high-speed ECL device having ECL compatible open-
emitter outputs. Pull-down resistors to the —5 V supply
are in resistor pack R2295. The ECL output levels are
converted to TTL levels by U2205 and U2206 and placed
on the C-DATA BUS.
An external voltage reference for the ADC is generated
by a circuit composed of operational amplifier U2202B and
Q2213. The + 5V reference voltage is converted to a
current by R2259 and applied to the inverting input of
U2202B. An extra current source is provided from the
+ 8.6 V supply via R2260 to reduce loading on the +5
VREF. The closed-loop gain of the stage is -0.4 for an
output voltage of -2 V at the emitter of Q2213.
ACQUISITION MEMORY
The Acquisition Memory system, shown on Diagram 17,
controls the movement of the digitized data from the A/D
Converter to the Acquisition Memory. The acquisition
mode controls the way the transfer occurs. Data may be
transferred directly to memory through the MIN/MAX
registers as either Odd and Even data for a single channel
acquisition or Channel 1 and Channel 2 data for dual
channel acquisitions. In the Min-Max Mode, a certain
number of data samples are compared for the highest and
lowest amplitude during the comparison period. The max
imum and minimum data values are transferred to the
Acquisition Memory.
Data is transferred through the A/D Buffer, the
MIN/MAX Registers, the Swap Registers, and finally into
Acquisition Memory in a pipeline fashion. Waveforms are
constantly sampled and digitized at the ADCLK rate, then
the resulting data byte representing the value of each
sample is latched into the A/D Buffer if the CONV clock is
20 MHz. Each succeeding sample clocked into the A/D
Buffer follows the previous data sample through the digital
devices of the acquisition system. Acquisition control
clocks that are copies of the SAVECLK with various
delays handle the data transfer timing.
A/D Buffer
A data byte from the A/D Converter is latched into A/D
Buffer U3229 on the rising edge of the convert (CONV)
clock. The data is immediately available on the G data bus
during normal operation because the buffer is enabled by a
HI from NAND-gate U3426D.
For testing and diagnostics purposes, the TEST signal
on pin 12 of NAND-gate U3426D is made LO by the
Microprocessor via the Acquisition Mode Register. That
isolates the A/D Buffer from the bus and enables the Diag
nostic Code Generator to place data on the G data bus to
the MIN/MAX Registers.
MIN/MAX Registers
Data is latched into the MIN/MAX Registers in four
different ways depending on the acquisition mode. The
MINCLK and MAXCLK clocking signals are selected by
MIN/MAX Clock Selector multiplexer U3309. The mode
selected determines the actual clock signals that latch
data into the MIN/MAX Registers.
For Sampling mode, the data is latched by ODDCLK
and ODDCLK to place either odd and even data from a
single channel or Channel 1 and Channel 2 data from both
channels into the registers. The timing of the data bytes is
evenly spaced in sampling mode (see Figure 3-7).
In X-Y mode for 20 ms per division and slower, both
channels are chopped to obtain the horizontal and vertical
deflection signals. The EVENCLK signal clocks the MIN
Register and ODDCLK signal clocks the MAX Register.
Selecting these clocks makes the time difference between
the two samples 100 ns. The last possible sample in a
Channel 1 SAVECLK period and the first possible Chan
nel 2 sample are saved as a pair. X and Y data are then
separated by one CONV clock period rather than the
longer (possibly much longer) SAVECLK clock period.
Min-Max mode generates the last two clocking modes.
The first is the Min-Max Initialization mode. For initializa
tion, the first data sample in a SAVECLK period is latched
into both the MIN and the MAX Registers at the same
time. This is the sample with which the remaining samples
taken during the SAVECLK period are compared. After
storing the initial data sample, the MIN/MAX Clock Selec
tor multiplexer (U3309) is switched.. it then passes the
NEWMIN and NEWMAX signals from the data Compara
tors, U3233 and U3235, to clock the MIN/MAX Registers.
COMPARATORS. Data bytes latched into the
MIN/MAX Registers are compared with each new data
byte latched in the A/D Buffer. If the data value is either
lower than the present data in the MIN Register or higher
than present data in the MAX Register, the appropriate
Comparator output pin goes HI. The comparison takes
some time after the clocking signals, so the MIN/MAX
Clock Selector Multiplexer is disabled from passing the
NEWMAX or NEWMIN until the CONV clock goes LO. By
that time, the comparator outputs have stabilized. If a
NEWMAX or NEWMIN has occurred, the new data byte is
latched into the appropriate register one-half a CONV
clock cycle after the data was latched into the A/D Buffer.
The Min-Max data comparisons for each saved data
byte continue for the duration of the SAVECLK period.
The minimum number of samples compared is 4 at 20 ms
per division. This corresponds to the number of CONV
clock periods possible at the fastest SAVECLK rate (a
3-30
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