access by the Microprocessor. The memory address to be
written to or read from is controlled by the Address
Counter.
Theory of Operation—2230 Service
Acquisition Memory Address Counter
The Address Counter contains three, 4-bit binary
counters (U3423, U3424, and U3425). They are preset-
table and cascaded to obtain a maximum count of 2048.
The last bit count from the last counter (U3425) is the
PREFULL signal, and when it goes HI the pretrigger por
tion of the record has been completed. When a triggered
acquisition mode is in effect, PREFULL qualifies the next
trigger received as a valid trigger point. For triggered
operation of the acquisition system, the counters are
preloaded with a count that causes the last bit to become
a 1 when the pretrigger portion of the memory is full. The
following data point pairs of a record are then stored start
ing at location 0 and continue up to the end of the record.
The end (ENDREC) is determined by the Record Counter
in the Digital Time Base circuitry (shown on Diagram 18).
While waiting for a trigger after the pretrigger part of
the record is filled, data pairs are continually written into
the essentially circular memory space to keep the stored
waveform data (pretrigger data) current. When the acquisi
tion becomes triggered, the Record Counter (Diagram 18)
starts counting the post trigger data pairs. At the end-of-
record count, ENDREC goes HI and the acquisition is
stopped. The Microprocessor then reads the address of
the last data byte pair that was stored. Using that address
and the known length of record for the type of acquisition
being done, the Microprocessor calculates the beginning
address for the record.
When a read of the memory is done, the Address
Counter is enabled for a parallel load of the location to be
read by the ACQSEL signal from the processor. The
beginning address of the record is the first address loaded
from the Microprocessor Address Bus, bits A1 through
A12. The least significant address bit (AO) is reserved for
selecting which of the memories is to be read. The
Microprocessor sequences through the addresses reading
out the data bytes. In ROLL and SCAN even though there
is a continual updating of the waveform seen on the crt,
the Microprocessor and Acquisition System are not
required to run in step at all times. Instead, the Micropro
cessor is allowed to carry out other processes as the data
pairs are being stored in memory. When a read is started,
the current address count is read and stored away. The
Microprocessor then loads the address of the next unread
data pair to begin reading data. Memory locations are then
read and transferred to the display RAM (Diagram 15). At
the end of the read, the address count is reset to the pre
viously stored address to resume storing more data pairs
into the Acquisition Memory.
Acquisition Memory Address Registers
These registers pass the address count onto the
Microprocessor data bus when enabled. Registers U3427
and U3428 are enabled during different I/O periods. The
lower seven bits of the address count and the SAVECLK
are buffered by U3427; the upper four bits of the address
count and four status bits (BTRIGD, TRIGD, BYTEINT,
and ENDREC) are buffered by U3428. SAVECLK is
checked because both sample data pairs are transferred in
parallel from the MIN/MAX Registers into the Acquisition
Memory, losing the trigger-point reference. However, the
samples stored in one half period of SAVECLK are stored
in the opposite memory half from the samples stored in
the other half period. The memory half that the trigger
must be associated with is determined by the state of
SAVECLK at the end of the acquisition.
The two address registers are read by the Microproces
sor, as the result of an interrupt, to determine the cause of
an interrupt. If the ENDREC bit is LO, the address of the
end of the waveform record is stable because the acquisi
tion stopped. In that case, the Microprocessor must read
the address and store it. To do a memory read, the
Microprocessor must change the count of the Address
Counters. After a BYTEINT read has been done to
transfer more waveform data to the display RAM to
update the display, the stored address count is restored to
the Address Counter to allow the acquisition to continue.
DIGITAL TIME BASE
Clock Generator
Accurate clock signals are needed to transfer the data
and to control the timing of each operation. The main
clocking signals are produced by an oscillator and clock
generator circuit. A 40 MHz signal is produced by crystal
oscillator Y4100. The 40 MHz signal clocks all the flip-flops
in the Clock Generator, setting the clock edge timing of all
the other clocks. In the following description, refer to the
clock timing diagram, Figure 3-10.
Flip-flop U4102A divides the 40 MHz input clock by
two. The 20 MHz Q output goes to the Microprocessor
clock divider for timing the processor operations. The
20 MHz (I Converter) and is one input to the Clock state
machine (formed by the logic gates of U3112B, C,
U3113C, U4101B, and flip-flops U4118A, U4102B and
U4104A). Use of the state machine allows the choice of a
CONV clock rate of either 20 MHz (the same as the
ADCLK rate) or 10 MHz (one-half the ADCLK rate).
The final flip-flop circuit (U4104A) in the Clock Genera
tor produces the WRITECLK and WRITECLK signals at
one-half the selected CONV clock rate. The flip-flop is held
3-38
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