Options—2230 Service
All of the signal lines that are at GPIB levels are pro
tected by diode arrays CR1321, CR1322, and zener diode
VR1321. These networks clip voltage transients greater
than +6.8 volts or less than —0.6 volts.
Connector J1314 is a standard GPIB interface
connector.
Clock Divider and Diagnostic Latch
U1335 is a dual J-K flip-flop that performs two indepen
dent functions. U1335A divides the 6.7 MHz clock by two
for GPIB controller U1351. U1335B provides a one-bit
latch for diagnostic use. When its enable (clock), U1335B
pin 12, is strobed LO, the data on BDO is latched.
Parameter Buffer
Parameter buffer U1322 provides an eight-bit input port
for selecting parameters associated with the GPIB option
such as address and terminator. It consists of U1322,
SI321, and part of resistor pack R1322. The switch is
sensed by enabling buffer U1322 which gates its inputs
onto the data bus. Bit 7 is used to sense TR, U1351 pin
39, for diagnostic use.
Status Buffer
Status buffer U1323 is used to sense three of the GPIB
PARAMETER switch positions as well as miscellaneous
other signals. Buffer circuitry consists of U1323, S1321,
R1321, and part of resistor pack R1322. Status buffer
functions are shown in Table 7-35.
Table 7-35
GPIB Status Buffer Functions
BIT
Signal Name Function
Bit 0 PWR INT
Power going down interrupt
Bit 1 +5VP
Logic HI
Bit 2
TRIG
GPIB chip diagnostic
Bit 3
PARAMETER SWITCH position 8
Bit 4
PARAMETER SWITCH position 10
Bit 5
PARAMETER SWITCH position 9
Bit 6
+ 5 V p
Logic HI
Bit 7 DIAG
Diagnostic latch
OPTION 12
THEORY OF OPERATION
The RS-232-C communication option (see Diagram 23)
provides a general-purpose interface for the exchange of
waveforms and instrument-state information. It replaces
the XY Plotter board of the standard instrument but
includes the XY Plotter circuitry. The following discussion
refers only to the RS-232-C portion of the board.
The option includes 64K bytes of ROM, 2K bytes of
RAM, and an RS-232-C interface. Supporting the RS232
port are two 8-bit input ports for status signals and
parameter switches, and a 4-bit output port used mainly
for interrupt masking. The remaining circuitry either
decodes addresses or buffers signals.
Microprocessor bus signals are extended to this board
through W8101. The address bus, data bus, bus control
signals, several address decode lines, and power supplies
all pass through this connector.
Bus Buffers
The address lines are buffered by U1241 and U1233.
These buffers are always enabled. Data bus buffer U1231
is bidirectional. It isolates the option from the storage
board and improves signal driving capabilities. Also
buffered are the RD (U1233), WR (U1234D), and RESET
(U1244E) signals.
Address Decoding
All addresses in the COM-SEG range (80000H to
BFFFFH) are used by the option. Several addresses in the
l/O-SEG range (40000H to 7FFFFH) are used by option I/O
circuitry. Table 3-1 lists the actual addresses used.
Primary address decoding is accomplished by U1245. It
provides a one-of-eight, low-asserting signal when BA12,
BA13, 10 SEC and BLKO, are all LO. Address lines BA3,
BAS, and BA7 are decoded to produce eight strobes.
Three of the strobes are used to enable UART U1251,
parameter buffer U1222, and Status buffer U1223. A
fourth strobe is gated with BWR at U1234A to produce a
write strobe for the interrupt mask latch (U1236). Also
generated by U1245 is a signal that is LO whenever one
of the strobes is enabled and BA8 is LO. This signal is
gated with COM SEG and DEN in U1232A to produce an
enable ior the data bus buffer (U1231).
The ROM and RAM enable signals are generated by
U1235. One half of U1235 is enabled by C<5m SEG. It
decodes BLKO and BLK1 into four strobes, two are wire-
ANDed together to produce the ROMEN enable for the
7-41
To Next Page
Loading...
Need help?
General
