Theory of Operation— 2230 Service
U6305 pin 14. That signal in turn is controlled by the
PLT-EN signal (U6301B pin 9) that switches section B of
multiplexer U6301. When displaying storage waveforms
and readout characters, the PLT-EN signal is not active,
and the VECT SMPL signal is switched to control the S/H
circuit. For producing X-Y Plots, U6301C is activated, and
the VECT SMPL signal drives the X-Y Plotter Pen-Down
circuit (shown on Diagram 22).
SAMPLE INTEGRATOR. During digital storage
waveform displays, the S/H circuit and the Y-Integrating
circuit formed by U6307 and associated components pro
duce either vectors or dots. When U6301C connects
pin 13 to pin 14, U6307 integrates each step output of the
S/H circuit into a smooth ramp signal. This integrated sig
nal is the vertical deflection signal (still single-ended) that
connects the data points of the stored waveform display.
When the user selects either dot displays or X-Y Mode,
multiplexer U6301C connects pin 12 to pin 14. The long
time constant integrating function of U6308 is switched
out, and U6307 acts as an amplifier only for the voltage
being held by the S/H circuit, causing the crt display to be
dots. For readout character displays both during STORE
and NONSTORE modes, the S/H and integrator work only
in the vector mode because readout characters are vector
displays.
The integrator output is subtracted from the input volt
age at all times. When VECT SMPL goes LO, the
difference value is sampled and held by S/H U6305. The
held voltage value sets the slope of the integrator and
effectively "connects the dots” since the slope of the out
put vector is proportional to the difference between the
input voltage and the output voltage of the integrator.
Diode clamps CR6301, CR6303, CR6305, and CR6307
prevent voltage transients that could cause U6301C latch
up.
Vector Am plifiers
The integrator outputs are applied to vector amplifiers
U6401 and U6402, which are differential voltage-to-current
converters. Their outputs are differential currents which
are sent to the main deflection multiplex circuitry via J6410
and the I/O wiring harness. Vertical positioning information
is processed by display controller U9208, but horizontal
position information is not. Therefore the horizontal posi
tion voltage is applied to U6402D to affect horizontal posi
tion control of stored waveforms. At times when readout
characters are being drawn, this position signal is shunted
by transistor U6403A to reduce the positioning effect on
the characters. This action is controlled by the HPOS-DlS
signal from the display controller.
Plot Drive
When plot mode is on, the display controller activates
the PLT-EN signal, causing U6301B to apply the
VECT-SMPL signal to the PEN-DN line via U6404A and
U6402E, and the display controller internal modes change
so that VECT-SMPL provides the pen down control func
tion. The PEN-DN signal is sent via J6420 to the Z-axis
section and to the X-Y board or communication option
board (if installed). When U6301B activates plot mode,
Q6301 pulls the sample control lines of U6305 and U6306
LO putting them in tracking mode. This closes the vector
generator feedback loops regardless of vector/dot mode
selection. The PLT-EN signal also turns on operational
transconductance amplifiers U6404A, B, and C via transis
tor U6403E. Normally, their outputs are off, the plotter sig
nals are zero (held at ground by R6433, R6434). In plot
mode they turn on and act as voltage followers for the
vector signals (Y POINT, X POINT, and PEN). The "Y”
amplifier input is connected ahead of the Y vector genera
tor to preserve the ±2.5 V range and correct polarity.
The X-PLOT and Y-PLOT signals are sent via J6420 to the
X-Y board or communication option board (if installed).
Readout O ff Detector
To detect when the Storage/Readout Intensity knob is
at its counterclockwise end, U6405A (Diagram 20) moni
tors the readout (RO) voltage from J6410. Since RO volt
age is normally negative, but goes slightly positive at the
end of its rotation, U6405A output will go positive, turning
on transistor U6403B, causing the NO-RO line to be LO.
This signal is sent to the I/O board as status information.
Signal Conditioning
The signals ARES1, A-RES2, B-RES, and B-CAPS on
J6420 come from the Sweep Interface board. They are
encoded analog currents which contain most of the infor
mation about the positions of the A and B Timing
switches. Since the sum of the possible changes in these
currents is larger than U6302 (5V REF) can accommodate,
U6405B (Diagram 21) is used to buffer the 5V reference to
supply the termination resistors (Diagram 20). As these
currents change, the resulting voltages are measured by
the Status A/D (Diagram 19) so that the Microprocessor
can determine the state of the timing switch.
I/O and Vector Generator Board Power
D istribution
±15 VOLT POWER SUPPLYS. U6305 and U6306
operate from ±15 Volt supplies. These are generated by
flyback converters (see Diagram 21) consisting of U6202A,
U6202B, Q6202, Q6203, and associated circuitry. The
comparators in U6202 form oscillators which drive the
switch transistors to alternately store and unload energy in
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