Theory of Operation—2230 Service
ac coupled, the input signal must go through dc-blocking
capacitor C2. The blocking capacitor stops the dc com
ponent of the input signal from reaching the Attenuator cir
cuit. When switched into the signal path, attenuators ATI
and AT2 attenuate the input signal by factors of 100 and
10 respectively. When SI is set to GND, the input of the
Buffer Amplifier is connected to ground. This provides a
ground reference for the analog display and the Micropro
cessor without removing the applied signal from the input
connector. The coupling capacitor precharges through R2,
R4, and R8 to prevent large trace shifts when switching
from GND to AC.
A probe coding ring on the CH 1 OR X input connector
is used to read the attenuation factor of the attached
probe to automatically adjust the VOLTS/DIV scale factors
in the readout. The default setting is for XI attenuation
when either coaxial cables or uncoded probes are con
nected to the vertical inputs.
Buffer Amplifier and Low-Im pedance Attenuator
The Buffer Amplifier presents a high-impedance, low-
capacitance load to the signal from the High-Impedance
Attenuator and a low output impedance to the Low-
Impedance Attenuator. The dual-path buffer amplifier (slow
path and fast path) combines good dc stability with high
speed performance.
The input signal goes to the gate of source-follower
Q13 through R6 and C6, the fast path, and to the inverting
input of operational amplifier U10 from the resistive
voltage divider, formed by R3 and R5, the slow path.
Source-follower Q13 and emitter-follower Q18 have high-
impedance inputs that isolate the applied signal from the
loading effects of the Low-Impedance Attenuator. A volt
age divider formed by R46, R47, and R48 at the emitter
output of Q18 applies feedback to the noninverting input
of slow-path amplifier U10. The two input voltages to
amplifier U10 are compared, and the conductivity of
current-source transistor Q15 is changed to correct for
any frequency-gain error at the source of Q13. The
bandwidth of U10 is limited by capacitor CIO so that the
slow path responds only to frequencies below 100 kHz,
Input offset voltage compensation for U10, provided by
R10, eliminates trace shift between VCLTS/DIV switch
settings. Gain in both paths is matched by adjusting
MF/LF Gain Bal potentiometer R47. The path gains then
remain matched by the corrective action of U10 and Q15 if
gain differences in the two paths start to develop.
Low-Impedance Attenuator R19 divides down the
Buffer Amplifier output signal for application to Paraphase
Amplifier U30. The attenuator’s output impedance is 75
ohms at all VOLTS/DIV switch settings. The VOLTS/DIV
switch (S10) determines whether the Paraphase Amplifier
receives a signal attenuated by a factor of 1 (no attenua
tion), 2, 4, or 10.
Paraphase Amplifier
Paraphase Amplifier U30 converts the single-ended sig
nal from the Low-Impedance Attenuator into a differential
signal for the Vertical Preamplifier. Included in the circuitry
is switching that provides extra gain for the 2 mV position
of the VOLTS/DIV switch, adjustments for amplifier dc bal
ance, and circuitry for the Variable Volts/Div function.
Additionally, Channel 2 Paraphase Amplifier U80 contains
circuitry to invert the Channel 2 display.
The signal from the Low-Impedance Attenuator goes to
the base of one transistor in U30. The other input transis
tor is biased by the divider network formed by R30, R31,
and R33 to a level that produces a null between the out
puts of U30 (no trace shift on the crt screen) when the
VOLTS/DIV control is switched between 5 mV and 2 mV.
Emitter current for the two input transistors is supplied by
R21, R22, R23, and VAR-BAL potentiometer R25. Resis
tor R29 is the gain-setting resistor between the two
emitters. High-frequency compensation of the amplifier is
provided by the series combination of R27 and C27 shunt
ing R29. In the 2 mV position, amplifier gain is increased
because contact 15 of SI 0 is closed to place 2 mV Gain
potentiometer R26 and compensating capacitor C26 in
parallel with R29.
The collector current from the two input transistors
serves as emitter current for the two differential output
transistor pairs. Base-bias voltages for the two output
pairs are developed by the divider network formed by R39,
R41, R42, and Variable Volts/Div potentiometer R43. The
transistors of U30 have matched characteristics, so the
ratio of currents in the two 1C diodes connected to pin 11
determines the current ratios in the output transistor pairs.
As Variable Volts/Div potentiometer R43 is rotated from
calibrated to uncalibrated, the conduction level of the
transistors connected to R35 increases. Since the transis
tor pairs are cross-connected, the increased conduction in
one pair subtracts from the output current produced by
the transistor pair connected to R38, and the overall gain
of the amplifier decreases. VAR-BAL potentiometer R25 is
adjusted to balance the amplifier for minimal dc trace shift
as the Variable Volts/Div control is rotated.
Incorporated in the Channel 2 Paraphase Amplifier is
circuitry that allows the user to invert the polarity of the
Channel 2 signal. When INVERT switch S90 is out, the
transistor pairs in U80 are biased as they are in U30, and
CH 2 trace is not inverted. For the IN position of S90, con
nections to the bases of the output transistor pairs are
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