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4.26 CSI Expansion Connector..............................................................................................................................................81

5 Revision History................................................................................................................................................................... 83

List of Figures

Figure 1-1. Thermal Caution........................................................................................................................................................5

Figure 2-1. J721E EVM Board.....................................................................................................................................................6

Figure 2-2. System Architecture Interface................................................................................................................................... 7

Figure 2-3. J721E EVM Board Identification (SOM, CPB, QP Ethernet).....................................................................................8

Figure 2-4. J721E SOM Component Identification...................................................................................................................... 9

Figure 2-5. Jacinto7 Common Processor Component Identification......................................................................................... 10

Figure 2-6. Quad Ethernet Component Identification.................................................................................................................11

Figure 3-1. Connector Used for Power Input............................................................................................................................. 12

Figure 3-2. Power ON/OFF Switch............................................................................................................................................ 13

Figure 3-3. Power ON/Fault LEDs............................................................................................................................................. 14

Figure 3-4. Power Status LEDs................................................................................................................................................. 15

Figure 3-5. EVM Push Buttons.................................................................................................................................................. 17

Figure 3-6. EVM Configuration DIP Switch................................................................................................................................18

Figure 3-7. BOOT Switches Provided on the Processor Card...................................................................................................21

Figure 3-8. JTAG Mux................................................................................................................................................................23

Figure 4-1. J721E EVM Functional Block Diagram................................................................................................................... 26

Figure 4-2. Quad Port Ethernet Expansion Functional Block diagram...................................................................................... 27

Figure 4-3. J721E SOM Power Distribution Block Diagram...................................................................................................... 31

Figure 4-4. Power ON Sequencing............................................................................................................................................32

Figure 4-5. Voltage Supervisor Circuit....................................................................................................................................... 33

Figure 4-6. LPDDR4 IO Voltage Selection Circuit..................................................................................................................... 34

Figure 4-7. EVM Reset Architecture.......................................................................................................................................... 38

Figure 4-8. EVM Clock Architecture.......................................................................................................................................... 39

Figure 4-9. J721E SoC Primary Clock.......................................................................................................................................40

Figure 4-10. J721E SoM LPDDR4.............................................................................................................................................42

Figure 4-11. J721E SoM OSPI and Hyper Flash....................................................................................................................... 43

Figure 4-12. UFS Memory Block Diagram.................................................................................................................................44

Figure 4-13. eMMC Memory Block Diagram............................................................................................................................. 45

Figure 4-14. micro-SD Card Block Diagram.............................................................................................................................. 46

Figure 4-15. MCU Gigabit Ethernet Block................................................................................................................................. 48

Figure 4-16. MCU Ethernet PHY Settings................................................................................................................................. 49

Figure 4-17. Quad-SGMII Board I2C......................................................................................................................................... 51

Figure 4-18. QSGMII Ethernet PHY Settings............................................................................................................................ 52

Figure 4-19. PCIe Interface for SERDES0................................................................................................................................ 53

Figure 4-20. PCIe SMBUS Block Diagram................................................................................................................................ 53

Figure 4-21. 1L-PCIe Root Complex/Endpoint Selection Circuit............................................................................................... 54

Figure 4-22. USB2.0 Header Connection.................................................................................................................................. 55

Figure 4-23. PCIe Interface for SERDES1................................................................................................................................ 56

Figure 4-24. 2L-PCIe Root Complex/Endpoint Selection Circuit............................................................................................... 56

Figure 4-25. PCIe Interface for SERDES2................................................................................................................................ 58

Figure 4-26. USB3.1 Type C Interface.......................................................................................................................................59

Figure 4-27. Type C Power Delivery Current Settings...............................................................................................................59

Figure 4-28. USB Hub Reference Clock Circuit.........................................................................................................................60

Figure 4-29. USB Hub Settings Circuit...................................................................................................................................... 60

Figure 4-30. USB1 ID Setting for HUB...................................................................................................................................... 60

Figure 4-31. MCU CAN0 Interface.............................................................................................................................................61

Figure 4-32. CAN Wake Push Button........................................................................................................................................ 62

Figure 4-33. CAN Header Connections to DB9/Test Instrument............................................................................................... 63

Figure 4-34. FPD-Link UB926 ID Setting Circuit....................................................................................................................... 64

Figure 4-35. FPD-Link UB926 Mode Selection Circuit.............................................................................................................. 64

Figure 4-36. FPD-Link UB941A Device Settings Circuit............................................................................................................65

Figure 4-37. Audio Port Interface Assignment...........................................................................................................................67

Figure 4-38. Display Port Block Diagram...................................................................................................................................68

Figure 4-39. MLB Interface Connector...................................................................................................................................... 69

Figure 4-40. ADC Interface Connector...................................................................................................................................... 70

Figure 4-41. RTC Block Diagram...............................................................................................................................................71

Figure 4-42. Apple Authentication Block Diagram..................................................................................................................... 72

Figure 4-43. Expansion Board Interface Connectors.................................................................................................................73

Figure 4-44. CDCI I2C Isolation Circuit..................................................................................................................................... 78

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2 Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM) SPRUIS4D – MAY 2020 – REVISED MARCH 2022

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