Texas Instruments J721E User Manual

Figure 4-45. Dual I/O Voltage Selection for CSI Expansion Interface....................................................................................... 81
List of Tables
Table 1-1. REACH Compliance................................................................................................................................................... 6
Table 3-1. Recommended External Power Supply.................................................................................................................... 12
Table 3-2. Power LED Status.....................................................................................................................................................14
Table 3-3. Power LEDs.............................................................................................................................................................. 15
Table 3-4. Power Test Points..................................................................................................................................................... 16
Table 3-5. EVM Push Buttons....................................................................................................................................................17
Table 3-6. EVM Configuration Switch Function......................................................................................................................... 19
Table 3-7. EVM Configuration Switch Function......................................................................................................................... 20
Table 3-8. Wakup Boot Mode Switch (SW9)..............................................................................................................................21
Table 3-9. Main Boot Mode Switch (SW8)................................................................................................................................. 21
Table 3-10. UART Port Mapping................................................................................................................................................22
Table 3-11. JTAG 1:2 Mux selection.......................................................................................................................................... 23
Table 3-12. TI 60 pin Connector (J16) Pinout............................................................................................................................ 24
Table 3-13. cTI20 Pin Connector (J1-Refer PROC081E2 SCH) Pinout.................................................................................... 25
Table 3-14. TI14 Pin Connector (J2-Refer PROC081E2 SCH) Pinout...................................................................................... 25
Table 4-1. J721E EVM Interface Mapping................................................................................................................................. 28
Table 4-2. J721E EVM I2C Table...............................................................................................................................................29
Table 4-3. J721E SoC - GPIO Mapping Table........................................................................................................................... 30
Table 4-4. DDR I/O Voltage Selection........................................................................................................................................34
Table 4-5. J721E SoC S2R Logic Flow......................................................................................................................................35
Table 4-6. J721E SoC S2R Logic Flow......................................................................................................................................35
Table 4-7. INA Devices I2C Slave Address............................................................................................................................... 36
Table 4-8. External Power Monitor Header Pinouts...................................................................................................................37
Table 4-9. Processor’s Secondary/SERDES Ref Clock.............................................................................................................41
Table 4-10. EVM Peripheral Ref Clock...................................................................................................................................... 41
Table 4-11. Board ID Memory Header Information.................................................................................................................... 47
Table 4-12. Clock Source Selection...........................................................................................................................................50
Table 4-13. Reference Clock Selection for PCIe Host Operation.............................................................................................. 54
Table 4-14. Reference Clock Selection for PCIe Endpoint Operation....................................................................................... 54
Table 4-15. Resistors for Selecting PCIe Card Host or Device Operation.................................................................................55
Table 4-16. Reference Clock Selection for PCIe Host Operation.............................................................................................. 57
Table 4-17. Reference Clock Selection for PCIe Endpoint Operation....................................................................................... 57
Table 4-18. Resistors for Selecting PCIe Card Host or Device Operation.................................................................................57
Table 4-19. FPD Audio Deserializer HSD Connector Pinout..................................................................................................... 65
Table 4-20. DSI to FPD Serializer HSD Connector Pinout........................................................................................................ 65
Table 4-21. MCASP/TRACE - 1:3 MUX: Truth Table................................................................................................................. 66
Table 4-22. Config Table
(1)
.......................................................................................................................................................66
Table 4-23. MLB Header Pinout.................................................................................................................................................69
Table 4-24. MCU I3C Header J33 Pinout.................................................................................................................................. 70
Table 4-25. MAIN I3C Header J32 Pinout..................................................................................................................................70
Table 4-26. ADC Header J23 Pinout..........................................................................................................................................71
Table 4-27. APPLE AUTH Header J9 Pinout.............................................................................................................................72
Table 4-28. APPLE AUTH Footprint U108 Pinout......................................................................................................................73
Table 4-29. EVM Expansion Connector J46 Pinout...................................................................................................................74
Table 4-30. EVM Expansion Connector J51 Pinout...................................................................................................................76
Table 4-31. ENET Expansion Board Power Test Points............................................................................................................ 77
Table 4-32. ENET Expansion Connector J10 Pinout................................................................................................................. 79
Table 4-33. CSI Expansion Connector J52 Pinout.....................................................................................................................82
Table 4-34. CSI Expansion Connector J48 Pinout.....................................................................................................................82
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SPRUIS4D – MAY 2020 – REVISED MARCH 2022
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Texas Instruments J721E Specifications

General

Brand	Texas Instruments
Model	J721E
Category	Motherboard
Language	English