GE Marquette MAC 5000 User Manual

Revision B 5-7
CPU Theory of Operation: Theory of Operation
MAC 5000 resting ECG analysis system
2000657-002
Bootstrap Instruction Unpacker
The FPGA provides an interface that unpacks instructions to start the
CPU from the byte wide SmartMedia card. Early during system startup,
Curly extracts instruction bytes from the card and presents them to the
FPGA for unpacking. Each instruction byte is loaded into the FPGA via
the signal ByteRdy. Curly asserts the SmartMedia nFRD signal while
simultaneously asserting ByteRdy to improve transfer rate. Curly
generally does not examine the instruction bytes (a more complete
explanation of the bootstrap process is presented in Curly’s source
code). When four bytes (one instruction) have been loaded into the
FPGA, Curly asserts WordRdy and the FPGA places the unpacked
instruction on the StrongARM data bus and negates nWait, allowing the
StrongARM to fetch and execute the instruction. In this fashion the
initial bootstrap loader is loaded into main DRAM. Curly’s read rate is
far too low to load all code from the card, so only a simple bootstrap
program is copied to DRAM. This program contains code that allows the
StrongARM to access the SmartMedia card directly through the FPGA.
Once that initial bootstrap is loaded, Curly disconnects from the circuit
(tri states all pins except nReset) and stops its internal clock. StrongARM
execution is transferred to the bootstrap loader in DRAM and the
remaining system code is read from the card at high speed. The byte
unpacker lies dormant until the next startup.
EDO DRAM Controller
MAC 5000 main memory is comprised of 4MBytes (2 1M x 16 devices) of
EDO DRAM. The FPGA provides a burst interface to DRAM that allows 8
word bursts at 4-1-1-1-1-1-1-1 clocks. Write bursts run at 4-2-2-2-2-2-2-
2 clocks. Single read/write accesses take 5 clocks. Refresh cycles (5
clocks) are queued approximately every 10 microseconds for an
overhead of 2 percent. The control of DRAM nCAS requires logic delays
shorter than can be obtained in the FPGA. For this reason a 3.5ns PAL
provides the final stage of nCAS control. Enabling signals are provided
by the FPGA and the PAL anchors the final nCAS signals off the main bus
clock (nMCLK).
XBus Controller
To reduce loading on the high speed processor address and data busses,
a slow speed byte bus is provided for peripheral interface. The SuperIO
controller and SmartMedia card are both located on this bus. XBus is
decoupled from main bus traffic to reduce EMI. XBus data lines are only
active when an XBus device is being accessed. Unlike the 3.3V only main
data/address busses, XBus is compatible with both 5V and 3.3V logic.
StrongARM address lines A8..11 are buffered by the FPGA for use by
XBus devices. To reduce loading on A1..A3 which drive the DRAM burst
addresses, the low order address byte is not used by XBus. Starting XBus
addressing with A8 also produces SuperIO addresses which easily map
to their standard PC equivalents (simply append 00 to a PC SuperIO
address to get a MAC5000 SuperIO address).
LCD Controller VLB Bus Cycle
Interface
The LCD controller expects VESA local bus signaling, not StrongARM
bus signaling. The FPGA provides the necessary logic to interface the
StrongARM nMReq/nWait interface to the LCD controller’s nCS/nRdy/
nRdyRtn interface. The LCD controller does not support burst accesses .
Note: No LCD controller bus timeout logic is provided, so accesses to
unmapped regions of controller space will hang the system.

GE Marquette MAC 5000 Specifications

General

Brand	GE
Model	Marquette MAC 5000
Category	Medical Equipment
Language	English