Status Structure 8-7
Status byte register
The summary messages from the status registers and queues are used to set or clear the
appropriate bits (B0, B2, B3, B4, B5, and B7) of the status byte register. These summary bits do
not latch, and their states (0 or 1) are solely dependent on the summary messages (0 or 1). For
example, if the standard event register is read, its register will clear. As a result, its summary
message will reset to 0, which in turn will reset the ESB bit in the status byte register.
The bits of the status byte register are described as follows:
• Bit B0,
measurement status (MSB) — Set summary bit indicates that an enabled
measurement event has occurred.
• Bit B1
— Not used.
• Bit B2,
error available (EAV) — Set summary bit indicates that an error or status
message is present in the error queue.
• Bit B3,
questionable summary bit (QSB) — Set summary bit indicates that an enabled
questionable event has occurred.
• Bit B4, message
available (MAV) — Set summary bit indicates that a response message
is present in the output queue.
• Bit
B5, event summary bit (ESB) — Set summary bit indicates that an enabled standard
event has occurred.
• Bit B6,
request service (RQS)/master summary status (MSS) — Set bit indicates that
an enabled summary bit of the status byte register is set.
• Bit
B7, operation summary (OSB) — Set summary bit indicates that an enabled
operation event has occurred.
Depending on how it is used, bit B6 of the status byte register is either the request for service
(RQS) b
it or the master summary status (MSS) bit:
• When using the serial poll sequence of the power supply to obtain the status byte (a.k.a.
serial poll b
yte), B6 is the RQS bit. See “Serial Polling and SRQ” for details on using the
serial poll sequence.
• When using the *STB? command (see “Status byte and service request commands” on
page 8-9) to read the status byte, B6 is the MSS bit.
Test Equipment Depot - 800.517.8431 - 99 Washington Street Melrose, MA 02176
TestEquipmentDepot.com
To Next Page
Loading...
