Nvidia JETSON TX2 User Manual

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 65
Table 69. I2C Signal Connections
Module Pin Name
Type
Termination
Description
I2C_GP0_CLK/DAT
I/OD
1k pull-ups to VDD_1V8 on the module
General I2C 0 Clock\Data. Connect to CLK/Data pins of 1.8V devices
I2C_GP1_CLK/DAT
I/OD
1k pull-ups to VDD_3V3_SYS on the
module
General I2C 1 Clock\Data. Connect to CLK/Data pins of 3.3V devices.
I2C_GP2_CLK/DAT
I/OD
1k pull-ups to VDD_1V8 on the module
General I2C 2 Clock\Data. Connect to CLK/Data pins of 1.8V devices
I2C_GP3_CLK/DAT
I/OD
1k pull-ups to VDD_1V8 on the module
General I2C 3 Clock\Data. Connect to CLK/Data pins of 1.8V devices.
I2C_PM_CLK/DAT
I/OD
1k pull-ups to VDD_1V8 on the module
Power Mon. I2C Clock\Data. Connect to CLK/Data pins of 1.8V
devices
I2C_CAM_CLK/DAT
I/OD
1k pull-ups to VDD_1V8 on the module
Camera I2C Clock\Data. Connect to CLK/Data pins of any 1.8V devices
DP0_AUX_CH+/–
I/OD
See eDP/HDMI/DP sections for correct
termination
DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI).
Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI)
DP1_AUX_CH+/–
I/OD
See eDP/HDMI/DP sections for correct
termination
DP_AUX Channel (eDP/DP) or DDC I2C 2 Clock & Data (HDMI).
Connect to AUX_CH+/– (DP) or SCL/SDA (HDMI)
Note:
1. If some devices require a different voltage level than others connected to the same I2C bus, level shifters are required.
2. For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are
pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers.
De -bounce
The tables below contain the allow able De-bounce settings for the various I2C Modes.
Table 70. De-bounce Settings (Fast Mode Plus, Fast Mode & Standard Mode)
I2C Mode
Clock Source
Source Clock Freq
I2C Source Divisor
Sm/Fm Divisor
De-bounce Value
I2C SCL Freq
Fm+
PLLP_OUT0
408MHz
5 (0x04)
10 (0x9)
0
1016KHz
5:1
905.8KHz
7:6
816KHz
Fm
PLLP_OUT0
408MHz
5 (0x4)
26 (0x19)
7:0
392KHz
Sm
PLLP_OUT0
408MHz
20 (0x13)
26 (0x19)
7:0
98KHz
Note:
Sm = Standard Mode.
12.2 SPI
Jetson TX2/TX2i brings out three of the Tegra SPI interfaces.
Table 71. SPI Pin Descriptions
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
E3
SPI0_CLK
GPIO_SEN1
SPI 0 Clock
Display Connector
Bidir
CMOS  1.8V
F3
SPI0_CS0#
GPIO_SEN4
SPI 0 Chip Select 0
Bidir
CMOS  1.8V
E4
SPI0_MISO
GPIO_SEN2
SPI 0 Master In / Slave Out
Bidir
CMOS  1.8V
F4
SPI0_MOSI
GPIO_SEN3
SPI 0 Master Out / Slave In
Bidir
CMOS  1.8V
G13
SPI1_CLK
GPIO_CAM4
SPI 1 Clock
Expansion Header
Bidir
CMOS  1.8V
E14
SPI1_CS0#
GPIO_CAM7
SPI 1 Chip Select 0
Bidir
CMOS  1.8V
F14
SPI1_MISO
GPIO_CAM5
SPI 1 Master In / Slave Out
Bidir
CMOS  1.8V
F13
SPI1_MOSI
GPIO_CAM6
SPI 1 Master Out / Slave In
Bidir
CMOS  1.8V
H14
SPI2_CLK
GPIO_WAN5
SPI 2 Clock
Display/Camera Conns.
Bidir
CMOS  1.8V
G16
SPI2_CS0#
GPIO_WAN8
SPI 2 Chip Select 0
Bidir
CMOS  1.8V
F16
SPI2_CS1#
GPIO_MDM4
SPI 2 Chip Select 1
Bidir
CMOS  1.8V
H15
SPI2_MISO
GPIO_WAN6
SPI 2 Master In / Slave Out
Bidir
CMOS  1.8V
G15
SPI2_MOSI
GPIO_WAN7
SPI 2 Master Out / Slave In
Bidir
CMOS  1.8V

Nvidia JETSON TX2 Specifications

General

Brand	Nvidia
Model	JETSON TX2
Category	Microcontrollers
Language	English