Nvidia JETSON TX2 User Manual

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 95
20.0 APPENDIX E: JETSON TX2/TX2I PIN DESCRIPTIONS
Table 93. Jetson TX2/TX2i Connector (8x50) Pin Descriptions
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
A1
VDD_IN

Main power  Supplies PMIC & external
supplies
Main DC input
Input
5.5V-19.6V (TX2)
9.0V-19.0V (TX2i)
A2
VDD_IN
A3
GND

GND
GND

GND
A4
GND

GND
GND

GND
A5
RSVD

Not used



A6
I2C_PM_CLK
GEN8_I2C_SCL
PM I2C Clock
I2C (General)
Bidir
Open Drain  1.8V
A7
CHARGING#
(PMIC GPIO5)
Charger Interrupt
System
Input
CMOS  1.8V
A8
GPIO14_AP_WAKE_MDM
UFS0_RST
AP (Tegra) Wake Modem or GPIO
M.2 Key E
Output
CMOS  1.8V
A9
GPIO15_AP2MDM_READY
UFS0_REF_CLK
AP (Tegra) to Modem Ready or GPIO
Output
CMOS  1.8V
A10
GPIO16_MDM_WAKE_AP
GPIO_MDM2
Modem Wake AP (Tegra) or GPIO
Input
CMOS  1.8V
A11
JTAG_GP1
NVJTAG_SEL
JTAG General Purpose 1. Pulled low on
module for normal operation & pulled
high by test device for Boundary Scan
test mode.
JTAG
Input
CMOS  1.8V
A12
JTAG_TMS
JTAG_TMS
JTAG Test Mode Select
JTAG Header & Debug
Connector
Input
CMOS  1.8V
A13
JTAG_TDO
JTAG_TD0
JTAG Test Data Out
Output
CMOS  1.8V
A14
JTAG_RTCK

JTAG Return Clock
Input
CMOS  1.8V
A15
UART2_CTS#
UART2_CTS
UART 2 Clear to Send
M.2 Key E
Input
CMOS  1.8V
A16
UART2_RTS#
UART2_RTS
UART 2 Request to Send
Output
CMOS  1.8V
A17
USB0_EN_OC#
USB_VBUS_EN0
USB VBUS Enable/Overcurrent 0
USB 2.0 Micro AB
Bidir
Open Drain  3.3V
A18
USB1_EN_OC#
USB_VBUS_EN1
USB VBUS Enable/Overcurrent 1
USB 3.0 Type A
Bidir
Open Drain  3.3V
A19
RSVD

Not used



A20
I2C_GP1_DAT
GEN1_I2C_SDA
General I2C 1 Data
I2C (General)
Bidir
Open Drain  3.3V
A21
I2C_GP1_CLK
GEN1_I2C_SCL
General I2C 1 Clock
Bidir
Open Drain  3.3V
A22
GPIO_EXP1_INT
GPIO_MDM7
GPIO Expander 1 Interrupt or GPIO
GPIO Expander
Input
CMOS  1.8V
A23
GPIO_EXP0_INT
GPIO_MDM1
GPIO expander 0 Interrupt or GPIO
Input
CMOS  1.8V
A24
LCD1_BKLT_PWM
GPIO_DIS5
Display Backlight PWM 1
Display Connector
Output
CMOS  1.8V
A25
LCD_TE
GPIO_DIS1
Display Tearing Effect
Input
CMOS  1.8V
A26
GSYNC_HSYNC
GPIO_DIS4
GSYNC Horizontal Sync
Output
CMOS  1.8V
A27
GSYNC_VSYNC
GPIO_DIS2
GSYNC Vertical Sync
Output
CMOS  1.8V
A28
GND

GND
GND

GND
A29
SDIO_RST#
GPIO_WAN3
Secondary WLAN Enable
M.2 Key E
Output
CMOS  1.8V
A30
SDIO_D3
SDMMC3_DAT3
SDIO Data 3
SDIO
Bidir
CMOS  1.8V
A31
SDIO_D2
SDMMC3_DAT2
SDIO Data 2
Bidir
CMOS  1.8V
A32
SDIO_D1
SDMMC3_DAT1
SDIO Data 1
Bidir
CMOS  1.8V
A33
DP1_HPD
DP_AUX_CH1_HPD
Display Port 1 Hot Plug Detect
HDMI Type A Conn.
Input
CMOS  1.8V
A34
DP1_AUX_CH
DP_AUX_CH1_N
Display Port 1 Aux or HDMI DDC SDA
Bidir
AC-Coupled on Carrier
Board (eDP/DP) or Open-
Drain, 1.8V (3.3V tolerant -
DDC/I2C)
A35
DP1_AUX_CH+
DP_AUX_CH1_P
Display Port 1 Aux+ or HDMI DDC SCL
Bidir
A36
USB0_OTG_ID
(PMIC GPIO0)
USB 0 ID / VBUS EN
USB 2.0 Micro AB
Input
Analog
A37
GND

GND
GND

GND
A38
USB1_D+
USB1_DP
USB 2.0, Port 1 Data+
USB 3.0 Type A
Bidir
USB PHY
A39
USB1_D
USB1_DN
USB 2.0, Port 1 Data
Bidir
A40
GND

GND
GND

GND
A41
PEX2_REFCLK+
PEX_CLK2P
PCIe 2 Reference Clock+ (PCIe IF #1)
Unassigned
Output
PCIe PHY
A42
PEX2_REFCLK
PEX_CLK2N
PCIe 2 Reference Clock (PCIe IF #1)
Output
A43
GND

GND
GND

GND
A44
PEX0_REFCLK+
PEX_CLK1P
PCIe 0 Reference Clock+ (PCIe IF #0)
PCIe x4 Connector
Output
PCIe PHY
A45
PEX0_REFCLK
PEX_CLK1N
PCIe 0 Reference Clock  (PCIe IF #0)
Output
A46
RESET_OUT#
SYS_RESET_N
Reset Out. Reset from PMIC (through
diodes) to Tegra & eMMC reset pins.
Driven from carrier board to force reset
of Tegra & eMMC (not PMIC). An
external 100pull-up to 1.8V near
Tegra (module pin side) & external
pull-up to 1.8V on the other
side of a diode (PMIC side).
System
Bidir
CMOS  1.8V

Nvidia JETSON TX2 Specifications

General

Brand	Nvidia
Model	JETSON TX2
Category	Microcontrollers
Language	English