Xilinx ZC702 User Manual

ZC702 Board User Guide www.xilinx.com 16
UG850 (v1.7) March 27, 2019
Feature Descriptions
Device Configuration
Zynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure
and a secure boot. The PS is the master of the boot and configuration process. For a secure
boot, the PL must be powered on to enable the use of the security block located within the
PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC702 board supports these configuration options:
• PS Configuration: Quad SPI flash memory
• PS Configuration: Processor System Boot from SD Card (J64)
• PL Configuration: USB JTAG configuration port (Digilent module)
• PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
TIP: Designs using serial configuration based on Quad-SPI flash memory can take advantage of
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in Table 1-2 and SW10
as described in Programmable Logic JTAG Programming Options for PL configuration
details. SW10 is callout 23 in Figure 1-2.
Note:
For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoC
Technical Reference Manual (UG585) [Ref 2].
Table 1-2: Switch SW16 Configuration Option Settings
Boot Mode SW16.1 SW16.2 SW16.3 SW16.4 SW16.5
JTAG mode
(1)
00000
Independent JTAG mode
10000
Quad SPI mode
00010
SD mode
00110
MIO configuration pin
MIO2 MIO3 MIO4 MIO5 MIO6
Notes:
1. Default switch setting
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Xilinx ZC702 Specifications

General

Brand	Xilinx
Model	ZC702
Category	Motherboard
Language	English