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Xilinx ZC702 User Manual

Xilinx ZC702
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ZC702 Board User Guide www.xilinx.com 48
UG850 (v1.7) March 27, 2019
Feature Descriptions
GPIO DIP Switch
[Figure 1-2, callout 19]
Figure 1-23 shows the GPIO DIP switch circuit.
Table 1-25 lists the GPIO DIP switch connections to XC7Z020 SoC U1.
X-Ref Target - Figure 1-23
Figure 1-23: GPIO DIP Switch
Table 1-25: GPIO DIP Switch Connections to XC7Z020 SoC at U1
XC7Z020 (U1) Pin Net Name I/O Standard DIP Switch SW12 Pin
W6 GPIO_DIP_SW0 LVCMOS25 2
W7 GPIO_DIP_SW1 LVCMOS25 1
UG850_c1_23_032719
SDA02H1SBD
SW12
VADJ
4
3
GPIO_DIP_SW1
GPIO_DIP_SW0
R51
4.7kΩ
0.1
Ω
5%
R50
4.7kΩ
0.1
Ω
5%
GND
1
2
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Xilinx ZC702 Specifications

General IconGeneral
BrandXilinx
ModelZC702
CategoryMotherboard
LanguageEnglish

Summary

ZC702 Board Features and Overview

ESD Safety Precautions

Safety instructions for handling ESD-sensitive components.

Zynq-7000 SoC Details

SoC Architecture and Core Features

Details on the Zynq-7000 SoC, its architecture, and core components.

Device Configuration

How to configure the Zynq-7000 SoC boot process.

I/O Voltage Rails

Details on the voltage levels for different I/O banks.

DDR3 Component Memory

Information about the 1 GB DDR3 memory system.

USB 2.0 ULPI Transceiver

Information about the USB 2.0 PHY transceiver.

SD Card Interface

Details on the SD card slot and its connections.

Programmable Logic JTAG Options

Options for programming the PL via JTAG.

Clock Generation Sources

Information on the board's clock sources.

Ethernet PHY Functionality

Details on the 10/100/1000 MHz Tri-Speed Ethernet PHY.

USB-to-UART Bridge

Information on the USB-to-UART bridge device.

Board Switches and Controls

FPGA Mezzanine (FMC) Interface

Power Management System

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