ZC702 Board User Guide www.xilinx.com 2
UG850 (v1.7) March 27, 2019
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Revision History
The following table shows the revision history for this document.
Date Version Revision
05/24/2012 1.0
Initial Xilinx release.
10/08/2012 1.1
The board photo in Figure 1-2 was updated. Table 1-2, Switch SW16 Configuration
Option Settings was added. The part number in Quad-SPI Flash Memory changed
to N25Q128A13ESF40F. In Table 1-6, the J35 shunt controls OTG and Device mode.
The frequency jitter in System Clock changed from 20 ppm to 50 ppm. The action
description under Program_B Pushbutton changed. The 34 differential user-defined
signals are defined as 34 LA pairs, LA00–LA33, in LPC Connectors J3 and J4. In the
same section, 34 differential user-defined pairs changed to 68 single-ended or 34
differential user-defined signals. Appendix E, Regulatory and Compliance
Information now includes a link to the Declaration of Conformity and markings for
waste electrical and electronic equipment (WEEE), restriction of hazardous
substances (RoHS), and CE compliance.
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