Agilent Technologies Agilent 33500 Series User Manual

STATus Subsystem Introduction
l Enable register cleared by:
l STATus:Questionable:ENABle 0
l STATus:PRESet
l Power cycle
l *CLS does not clear enable register but it does clear event register.
l *RST does not affect this register.
l The Query reads the enable register and returns a decimal value equal to the binary-weighted sum of all bits set in
the register.ter. For example, if bit 0 (value 1) and bit 1 ( value 2) are enabled, the query returns +3.
STATus:QUEStionable[:EVENt]?
Queries the event register for the Questionable Data Register group. This is a read-only register; the bits are cleared
when you read the register.
Parameter Typical Return
(none) +512
Read the event register (bit 9 set):
STAT:QUES?
l Once a bit is set, it remains set until cleared by this query or *CLS.
l *RST, STATus:PRESet, and *PSC have no effect on this register.
l Query reads the event register and returns a decimal value equal to the binary-weighted sum of all bits set in the
register. For example, if bit 1 (value 2) and bit 9 ( value 512) are set, the query returns "+514".
290 Agilent 33500 Series Operating and Service Guide

Agilent Technologies Agilent 33500 Series Specifications

General

Brand	Agilent Technologies
Model	Agilent 33500 Series
Category	Inverter
Language	English