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Remote Control

1.6 Queues

The Model 2000 uses two queues, which are first-in, first-out (FIFO) registers:

 Output Queue - used to hold reading and response messages

 Error Queue - used to hold error and status messages

The status model (Figure 4-5) shows how the two queues are structured with

the other registers.

1.6.1 Output queue

The output queue holds data that pertains to the normal operation of the

instrument. For example, when a query command is sent, the response

message is placed on the Output Queue.

When data is placed in the Output Queue, the Message Available (MAV) bit in

the Status Byte Register sets. A data message is cleared from the Output

Queue when it is read. The Output Queue is considered cleared when it is

empty. An empty Output Queue clears the MAV bit in the Status Byte Register.

Read a message from the Output Queue by addressing the electronic load to

talk after the appropriate query is sent.

1.6.2 Error queue

The Error Queue holds error and status messages. When an error or status

event occurs, a message that defines the error/status is placed in the Error

Queue. This queue will hold up to 10 messages.

When a message is placed in the Error Queue, the Error Available (EAV) bit in

the Status Byte Register is set. An error message is cleared from the

Error/Status Queue when it is read. The Error Queue is considered cleared

when it is empty. An empty Error Queue clears the EAV bit in the Status Byte

following SCPI query commands and then addressing the electronic load to

talk:

:SYSTem:ERRor?.

1.7 Status Byte and Service Request (SRQ)

Service request is controlled by two 8-bit registers: the Status Byte Register

and the Service Request Enable Register.

1.7.1 Status Byte Register

The summary messages from the status registers and queues are used to set

or clear the appropriate bits (B0, B2, B3, B4, B5, and B7) of the Status Byte

ITech IT8731 Programming Guide

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