Chapter 6 Digital I/O
© National Instruments 6-17 X Series User Manual
DO Sample Clock Signal
The device uses the DO Sample Clock (do/SampleClock) signal to update
the DO terminals with the next sample from the DO waveform generation
FIFO.
You can specify an internal or external source for DO Sample Clock. You
can also specify whether the DAC update begins on the rising edge or
falling edge of DO Sample Clock. If the DAQ device receives a DO Sample
Clock when the FIFO is empty, the DAQ device reports an underflow error
to the host software.
Using an Internal Source
One of the following internal signals can drive DO Sample Clock:
• DI Sample Clock (di/SampleClock)
• DO Sample Clock (do/SampleClock)
• AI Sample Clock (ai/SampleClock)
• AI Convert Clock (ai/ConvertClock)
• AO Sample Clock (ao/SampleClock)
•Counter n Sample Clock
•Counter n Internal Output
•Frequency Output
• DI Change Detection output
Several other internal signals can be routed to DO Sample Clock through
internal routes. Refer to Device Routing in MAX in the NI-DAQmx Help or
the LabVIEW Help for more information.
Using an External Source
Use one of the following external signals as the source of DO Sample
Clock:
• PFI <0..15>
•RTSI <0..7>
•PXI_STAR
• Analog Comparison Event (an analog trigger)
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