USB and PCIe
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 20
Table 7-2. Jetson Orin NX USB 3.2 and PCIe Pin Description
Module Pin
Recommended
131 PCIE0_RX0_N
HS_UPHY0_L4_RX_
N
PCIe #0 Receive 0 (PCIe Ctrl #4 Lane 0)
PCIe x4
conn/device (i.e.
M.2 Key M)
Input PCIe PHY
133 PCIE0_RX0_P
HS_UPHY0_L4_RX_
P
137 PCIE0_RX1_N
HS_UPHY0_L5_RX_
N
PCIe #0 Receive 1 (PCIe Ctrl #4 Lane 1)
139 PCIE0_RX1_P
HS_UPHY0_L5_RX_
P
149 PCIE0_RX2_N
HS_UPHY0_L6_RX_
N
PCIe #0 Receive 2 (PCIe Ctrl #4 Lane 2)
151 PCIE0_RX2_P
HS_UPHY0_L6_RX_
P
155 PCIE0_RX3_N
HS_UPHY0_L7_RX_
N
PCIe #0 Receive 3 (PCIe Ctrl #4 Lane 3)
157 PCIE0_RX3_P
HS_UPHY0_L7_RX_
P
134 PCIE0_TX0_N
HS_UPHY0_L4_TX_
N
PCIe #0 Transmit 0 (PCIe Ctrl #4 Lane 0)
Output PCIe PHY
136 PCIE0_TX0_P HS_UPHY0_L4_TX_P
140 PCIE0_TX1_N
HS_UPHY0_L5_TX_
N
PCIe #0 Transmit 1 PCIe Ctrl #4 Lane 1)
142 PCIE0_TX1_P HS_UPHY0_L5_TX_P
148 PCIE0_TX2_N
HS_UPHY0_L6_TX_
N
PCIe #0 Transmit 2 (PCIe Ctrl #4 Lane 2)
150 PCIE0_TX2_P HS_UPHY0_L6_TX_P
154 PCIE0_TX3_N
HS_UPHY0_L7_TX_
N
PCIe #0 Transmit 3 (PCIe Ctrl #4 Lane 3)
156 PCIE0_TX3_P HS_UPHY0_L7_TX_P
181 PCIE0_RST*
GP184_PCIE4_RST_
N
PCIe #0 Reset (PCIe Ctrl #4). 4.7kΩ pull-up
to 3.3V on the module. Output when Jetson
Xavier NX is Root Port or input when
Jetson Xavier NX is Endpoint.
Bidir
Open
Drain 3.3V
180
PCIE0_CLKRE
Q*
GP183_PCIE4_
CLKREQ_N
PCIE #0 Clock Request (PCIe Ctrl #4).
47kΩ pull-up to 3.3V on the module. Input
when Jetson Xavier NX is Root Port or
output when Jetson Rey is Endpoint.
160 PCIE0_CLK_N
SF_PCIE4_CLK_N
HS_UPHY0_
REFCLK2_N
PCIe #0 Reference Clock controlled by on-
module mux by SoC GP21. When GP21 is
low, SF_PCIE4_CLK is selected (reference
clock when module is Root Port). When
GP21 is high, UPHY0_REFCLK2_IN is
selected (reference clock input when
module is an Endpoint).
Bidir PCIe PHY
162 PCIE0_CLK_P
SF_PCIE4_CLK_P
HS_UPHY0_
REFCLK2_P
167 PCIE1_RX0_N
HS_UPHY0_L3_RX_
N
PCIe #1 Receive 0 (PCIe Ctrl #1 Lane 0) Input PCIe PHY
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