Nvidia Jetson Orin NX User Manual

USB and PCIe
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 30
Figure 7-9. PCIe Root Port Connections Example
Jetson
SoC - PCIe
UPHY0
GP177_PCIE1_CLKREQ_N
GP178_PCIE1_RST_N
GP185_PCIE_WAKE_N
PEX
Ctrl
HS_UP HY 0_L 7_T X_ N/P
PCIe 0 Lane 3
PCIe 0 Lane 2
PCIe 0 Lane 1
PCIe 0 Lane 0
HS_UP HY 0_L7_RX_N/P
HS_UP HY 0_L 6_T X_ N/P
HS_UP HY 0_L6_RX_N/P
HS_UP HY 0_L 5_T X_ N/P
HS_UP HY 0_L5_RX_N/P
HS_UP HY 0_L 4_T X_ N/P
HS_UP HY 0_L4_RX_N/P
3.3V
180
181
179
PCIe 0 (Ctrl #4) –
PCIe x4 conn/device
(i.e. M.2 Key M)
4.7kΩ
47kΩ
154/156
155/157
148/150
149/151
140/142
137/139
134/136
131/133
SF_PCIE1_CLK_N/P
HS_UP HY 0_L3_RX_N/P
167/169
173/175
PCIe 0 (Ctrl #4)
–
PCIe x4 conn/device
(i.e. M.2 Key M)
HS_UP HY 0_L 3_T X_ N/P
172/174
PCIe 1 (Ctrl #1) –
PCIe x1 conn/device
(i.e. M.2 Key E)
GP183_PCIE4_CLKREQ_N
GP184_PCIE4_RST_N
182
183
PCIe 1 (Ctrl #1) –
PCIe x1 conn/device
(i.e. M.2 Key E)
4.7kΩ
47kΩ
Shared wake pin
HS_UPHY0_REFCLK2_ N/P
160/162
SF_PCIE4_CLK_N/P
Mux
SE L
GP21
GP 21
HS_UPHY0_REFCLK2/
SF_P CIE4_CL K Mux Control
Se e Note 1
Se e Note 2
SF_PCIE7_CLK_N/P
HS_UP HY 2_L1_RX_N/P
HS_UP HY 2_L 1_T X_ N/P
64/66
PCIe 1 L1
PCIe 2 (Ctrl #7) –
PCIe x2
Or
PCIe 2 (Ctrl #7)
–
PCIe x1 (La ne 0 ) a nd
PCIe 3 (Ctrl #9) –
PCIe x1 (Lane 1)
HS_UP HY 2_L0_RX_N/P
HS_UP HY 2_L 0_T X_ N/P
PCIe 1 L0
58/60
46/48
40/42
52/54
SF_PCIE9_CLK_N
SF_PCIE9_CLK_P
227
GP191_PCIE9_CLKREQ_N
GP192_PCIE9_RST_N
3.3V
47kΩ
4.7kΩ
47kΩ
PCIe 3 (Ctrl #9) –
PCIe x1)
GP187_PCIE7_CLKREQ_N
GP188_PCIE7_RST_N
PCIe 2 (Ctrl #7) –
PCIe x2 or x1)
4.7kΩ
47kΩ
221
219
225
223
PCIE2_TX1_N/P
PCIE2_RX1_N/P
PCIE2_TX0_N/P
PCIE2_RX0_N/P
PCIE2_CLK_N/P
PCIE3_CLK_N
PCIE3_CLK_P
229
UPHY2
PCIE0_TX3_N/P
PCIE0_RX3_N/P
PCIE0_TX2_N/P
PCIE0_RX2_N/P
PCIE0_TX1_N/P
PCIE0_RX1_N/P
PCIE0_TX0_N/P
PCIE0_RX0_N/P
PCIE0_CLK_N/P
CSI4_D3_N/P
CSI4_D1_N/P
CSI4_D0_N/P
CSI4_D2_N/P
CSI4_CLK_N/P
SDMMC_CMD
SDMMC_CLK
PCIE1_TX0_N/P
PCIE1_RX0_N/P
PCIE1_CLK_N/P
PCIE0_CLKREQ*
PCI E 0_RST*
PCIE1_CLKREQ*
PCI E 1_RST*
SDMMC_DAT1
SDMMC_DAT0
SDMMC_DAT3
SDMMC_DAT2
PCIE_WAKE*
PCIE2_CLKREQ*
PCI E 2_RST*
PCIE3_CLKREQ*
PCI E 3_RST*
Notes:
1. For Root Port operation, the mux should be set to output the SF_PCIE10_CLK signals. SoC
GP21 which is used for the mux select should be set low.
2. AC Capacitors required on RX lines on carrier board if connected directly to device. They
should not be on the carrier board if connected to PCIe connector, M.2 Key M, etc. In those
cases, the AC caps are on the board connected to those connectors.
3. See design guidelines for correct AC capacitor values.
4. The PCIe REFCLK inputs and CLK outputs comply to the PCIe CEM specification “REFCLK DC
Specifications and AC Timing Requirements.” The clocks are HCSL compatible.

Nvidia Jetson Orin NX Specifications

General

Brand	Nvidia
Model	Jetson Orin NX
Category	Computer Hardware
Language	English