Display
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 40
Table 9-2. DP and HDMI Pin Mapping
DP1_TXD3_P
DP1_TXD3_N
83
81
TXC+
TXC –
TX3+
TX3–
DP1_TXD2_P
DP1_TXD2_N
77
75
TX0+
TX0–
TX2+
TX2–
DP1_TXD1_P
DP1_TXD1_N
71
69
TX1+
TX1–
TX1+
TX1–
DP1_TXD0_P
DP1_TXD0_N
65
63
TX2+
TX2–
TX0+
TX0–
9.1 eDP and DP
The following figure shows a basic the DP and eDP connection example.
Figure 9-1. DP and eDP Connection Example
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
10 0k
Ω
VDD_3 V3 _SYS
10 0kΩ
VDD_3 V3 _EDP
DP
Conn
.
PWR
PWR_RET
HPD
AUXN
GND
AUXP
CEC_DP
MODE
LA NE _3 N
GND
LA NE _3 P
LA NE _2 N
GND
LA NE _2 P
LA NE _1 N
GND
LA NE _1 P
LA NE _0 N
GND
LA NE _0 P
1
3
5
11
7
9
13
15
17
19
2
10
12
6
8
14
16
18
4
20
Jetson
SoC – DP/HDMI
DP1_HPD
DP1_AUX_N
DP1_AUX_P
DP1_TXD3_N
DP1_TXD3_P
DP1_TXD2_N
DP1_TXD2_P
DP1_TXD1_N
DP1_TXD1_P
DP1_TXD0_N
DP1_TXD0_P
96
100
98
65
63
71
69
77
83
81
75
0. 1uF
VDD_3 V3 _SYS
BUCK_3V3_PG
VDD_1 V8
10 kΩ
Load Switch
EN
IN OUT
Lev el Shifte r
1.8V 3.3V
10 kΩ
HS_DISP0_HDMI_D2_DP0_P
HS_DISP0_HDMI_D2_DP0_N
HS_DISP0_HDMI_D1_DP1_P
HS_DISP0_HDMI_D1_DP1_N
HS_DISP0_HDMI_D0_DP2_P
HS_DISP0_HDMI_D0_DP2_N
HS_DISP0_HDMI_CK_DP3_P
HS_DISP0_HDMI_CK_DP3_N
SF_DPAUX01_P
SF_DPAUX01_N
GP7 4_ HPD0_ N
Notes:
1. Level shifter required on DP0_HPD to avoid the pin from being driven when Jetson Orin NX is
off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the
display). The reference design uses a BJT level shifter, and a resistor divider is needed. See
the reference design if a similar approach will be used.
2.
Load Switch enable is from powergood pin of main 3.3V supply.