Display
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 49
Max via distance from BGA
must be placed before pull-down
resistor
The distance between the AC cap and the
HDMI connector is not restricted.
PTH design
Micro-via design
Place cap on bottom layer if main route
above core
Place cap on top layer if main route
below core
GND (or PWR) void under/above the
cap is needed. Void size = SMT area +
1x dielectric height keepout distance
Pull-down Resistor (RPD), choke/FET
Must be placed after AC cap
Placement: See Figure 9-19
Same layer as AC cap. The FET and
choke can be placed on the opposite
PD
Max trace Rdc
Max trace length
600 or
1
≤20
Ω@100MHz
uH@DC-100MHz
mΩ
Can be choke or Trace. Recommended
option for HDMI2.0 HF1-9 improvement.
GND/PWR void under/above cap is
preferred
Common-mode Choke (Not recommended – only used if absolutely required for EMI issues)
See Chapter 17 for details on CMC if implemented.
ESD (On-chip protection diode can withstand 2kV HMM. External ESD is optional. Designs should include ESD footprint as a stuffing
option)
Max junction capacitance
(IO to GND)
e.g. Texas Instruments
TPD4E02B04DQAR
Pad right on the net instead of trace
stub
After pull-down resistor/CMC and
before RS
GND/PWR void under/above the cap is
needed. Void size = 1 mm x 2 mm for
Series Resistor (RS): Series resistor on P/N path for HDMI 2.0 but not required for HDMI 2.1 (Mandatory to meet HDMI 2.0
Compliance).
± 10%. 0ohm is acceptable if the design
passes the HDMI2.0 HF1-9 test.
Otherwise, adjust the R
S value to ensure
the HDMI2.0 tests pass: Eye diagram,
Vlow test and HF1-9 TDR test
After all components and before HDMI
connector
GND/PWR void under/above the R
S
device is needed. Void size = SMT area + 1x
dielectric height keepout distance.
Trace at Component Region
At component region (Microstrip)
Trace entering the SMT pad