Quectel SG368Z Series User Manual

Smart Module Series
SG368Z_Series_Hardware_Design 61 / 113
b) Control the differential impedance to 100 Ω ±10 %;
c) Control intra-lane length matching within 0.3 mm.
d) Control the length matching between clock signal traces and data signals traces within 12 mm.
4.10.3. LCM Interfaces
Table 26: Pins Description of LCM Interfaces
Pin Name
Pin No.
I/O
Description
LCD1_RST
322
DO
LCD1 reset
DSI0_CLK_N
37
AO
LCD0 MIPI clock (-)
DSI0_CLK_P
36
AO
LCD0 MIPI clock (+)
DSI0_LN0_N
47
AO
LCD0 MIPI lane 0 data (-)
DSI0_LN0_P
46
AO
LCD0 MIPI lane 0 data (+)
DSI0_LN1_N
42
AO
LCD0 MIPI lane 1 data (-)
DSI0_LN1_P
41
AO
LCD0 MIPI lane 1 data (+)
DSI0_LN2_N
32
AO
LCD0 MIPI lane 2 data (-)
DSI0_LN2_P
31
AO
LCD0 MIPI lane 2 data (+)
DSI0_LN3_N
27
AO
LCD0 MIPI lane 3 data (-)
DSI0_LN3_P
26
AO
LCD0 MIPI lane 3 data (+)
DSI1_CLK_N
33
AO
LCD1 MIPI clock (-)
DSI1_CLK_P
29
AO
LCD1 MIPI clock (+)
DSI1_LN0_N
43
AO
LCD1 MIPI lane 0 data (-)
DSI1_LN0_P
39
AO
LCD1 MIPI lane 0 data (+)
DSI1_LN1_N
38
AO
LCD1 MIPI lane 1 data (-)
DSI1_LN1_P
34
AO
LCD1 MIPI lane 1 data (+)
DSI1_LN2_N
28
AO
LCD1 MIPI lane 2 data (-)
DSI1_LN2_P
24
AO
LCD1 MIPI lane 2 data (+)

Quectel SG368Z Series Specifications

General

Brand	Quectel
Model	SG368Z Series
Category	Control Unit
Language	English