Xilinx AC701 User Manual

14 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
Chapter 1: AC701 Evaluation Board Features
DDR3 Memory Module
[Figure 1-2, callout 2]
The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module
(SODIMM). It provides volatile synchronous dynamic random access memory (SDRAM)
for storing user code and data. The SODIMM socket has a perforated EMI shield
surrounding it as seen in
Figure 1-2.
• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)
• Supply voltage: 1.5V
• Datapath width: 64 bits
• Data rate: up to 1,600 MT/s
The DDR3 interface is implemented across I/O banks 33, 34, and 35. An external 0.75V
reference VTTREF is provided for these banks. Any interface connected to these banks that
requires a reference voltage must use this FPGA voltage reference. The connections
between the DDR3 memory and the FPGA are listed in
Table 1-4.
Bank 34 FPGA_1V5 1.5V
Bank 35 FPGA_1V5 1.5V
Table 1-3: FPGA Bank Voltage Rails (Cont’d)
U1 FPGA Bank
Power Supply Rail
Net Name
Voltage
Table 1-4: DDR3 Memory Connections to the FPGA
FPGA Pin (U1)
Schematic Net
Name
I/O Standard
J1 DDR3 Memory
Pin Number Pin Name
M4 DDR3_A0 SSTL15 98 A0
J3 DDR3_A1 SSTL15 97 A1
J1 DDR3_A2 SSTL15 96 A2
L4 DDR3_A3 SSTL15 95 A3
K5 DDR3_A4 SSTL15 92 A4
M7 DDR3_A5 SSTL15 91 A5
K1 DDR3_A6 SSTL15 90 A6
M6 DDR3_A7 SSTL15 86 A7
H1 DDR3_A8 SSTL15 89 A8
K3 DDR3_A9 SSTL15 85 A9
N7 DDR3_A10 SSTL15 107 A10/AP
L5 DDR3_A11 SSTL15 84 A11
L7 DDR3_A12 SSTL15 83 A12_BC_N
N6 DDR3_A13 SSTL15 119 A13
L3 DDR3_A14 SSTL15 80 A14
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Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English