Xilinx AC701 User Manual

AC701 Evaluation Board www.xilinx.com 37
UG952 (v1.3) April 7, 2015
Feature Descriptions
PCI Express Edge Connector
[Figure 1-2, callout 12]
The 4-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a
Gen1 application and 5.0
GT/s for a Gen2 application. The PCIe transmit and receive
signal datapaths have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as
a 100Ω differential pair. The 7
series FPGAs GTP transceivers are used for multi-gigabit per
second serial interfaces.
The XC7A200T-2FBG676C FPGA (-2 speed grade) included with the AC701 board
supports up to Gen2 x4.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK0 pins of Quad 216. PCIE_CLK_Q0_P is connected to FPGA U1 pin F11, and
the _N net is connected to pin E11. The PCI Express clock circuit is shown in
Figure 1-20.
PCIe lane width/size is selected using jumper J12 (Figure 1-21). The default lane size
selection is 4-lane (J12 pins 3 and 4) jumpered).
Table 1-12, page 35 lists the PCIe edge connector connections.
For more information, see the 7 Series FPGAs Integrated Block for PCI Express v3.0 Product
Guide (PG054)
[Ref 8].
X-Ref Target - Figure 1-20
Figure 1-20: PCI Express Clock
X-Ref Target - Figure 1-21
Figure 1-21: PCI Express Lane Size Select Jumper J12
UG952_c1_18_100312
PCI Express
Four-Lane
Edge connector
GND
GND
A15
A13
A14
P1
REFCLK+
A12
GND
C188
0.01μF 25V
X7R
C189
0.01μF 25V
X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
PCIE_CLK_Q0_C_P
PCIE_CLK_Q0_C_N
OE
REFCLK-
UG952_c1_19_100312
PCIE_PRSNT_B
PCIE_PRSNT_X1
PCIE_PRSNT_X4
J12
1
3
2
4
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Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English