24 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
Chapter 1: AC701 Evaluation Board Features
The AC701 clocking diagram is shown in Figure 1-10. The FPGA logic clock source circuits
are detailed first after Figure 1-10, followed by the GTP clock sources circuitry descriptions
in the GTP Transceivers section.
M21 USER_CLOCK_P LVDS_25
U34
4 Si570 3.3V LVDS I2C Programmable Oscillator (Silicon
Labs). Default power-on frequency 156.250
MHz. See
Programmable User Clock Source, page 25.
M22 USER_CLOCK_N LVDS_25 5
P16 FPGA_EMCCLK LVCMOS33 U40 3
SiT8103 3.3V Single-Ended LVCMOS 90 MHz Fixed
Frequency Oscillator (SiTime). See System Clock
Source, page 25.
Table 1-8: AC701 Board Clock Sources (Cont’d)
FPGA
Pin (U1)
Schematic Net
Name
I/O Standard
Clock
Reference
Pin Description
X-Ref Target - Figure 1-10
Figure 1-10: AC701 Board Clocking Diagram
UG952_c1_110_012015
U1
Artix-7 FPGA
XC7A200T-2FBG676C
Bank 16
Bank 15
Bank 14
Bank 13
Bank 12
Bank 36
Bank 35
Bank 34
Bank 33
Bank 32
GTP Quad
216
GTP Quad
213
PCI Express
Connector
P1
User SMA
J31(P)/J32(N)
Si5324
Jitter Attenuator
CLK Multiplier
U24
GTP SMA
J25(P)/J26(N)
FMC Connector
(HPC)
J30
SI570
Programmable
Oscillator
U34
Default 156.25 MHz
ICS844021
125 Mhz Clock
U2
X6
Crystal
Oscillator
114.285 MHz
3
2
1
0
U3
0
1
2
3
U4
PCIE_CLK_Q0_P/N
SYSCLK_P/N
Pins R3,P3
System CLK
200 MHz
U51
EMCCLK
90 MHz
U40
Rec_Clock_C_P/N Pins D23,D24
SEP_MGT_CLK_SEL[1:0] Pins C24:B26
PCIE_MGT_CLK_SEL[1:0] Pins C26:A24
USER_CLOCK_N
FPGA_EMCCLK
USER_CLOCK_N/P
EPHYCLK_Q0_C_P/N Pins 7,6
SI5324_Out0_C_N/P Pins 29,28
Pins D4,D5
Pins B20,B21
SI532_Out1_C_P/N Pins 35,34
SMA_MGT_REFCLK_P Pin 1,1
SFP_MGT_CLK0_N/P Pins AA13,AB13
SFP_MGT_CLK1_N/P Pins AA13,AB13
Pins J23,H23
Pins 3
Pins M21,M22
NC
NC
I2C
I2C or SPI
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