Xilinx AC701 User Manual

70 www.xilinx.com AC701 Evaluation Board
UG952 (v1.3) April 7, 2015
Chapter 1: AC701 Evaluation Board Features
Figure 1-45 shows the power system for UCD90120A U9 controller #2 rails 1 through 5.
X-Ref Target - Figure 1-45
Figure 1-45: U9 Controller #2 UCD90120A Power System
UG952_c1_138_030615
UCD90120A
Controller
(Controller 2)
U9
1. Capacitors labled C
f
are bulk filter capacitors.
2. Voltage Sense is connected
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
GPIO (Out)
Input
Filter
LMZ31506
U56 (2.5V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
FMC_ADJ_SEL[1:0]
Rs 5mΩ
+12V
V
fb
VCCO_ADJ 2.5V
C
f
C
f
(1)
Notes:
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
LMZ31503
U57 (1.8V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
FPGA_1V8 1.8V
C
f
C
f
VCC1V8 1.8V
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
LMZ31506
U58 (3.3V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
FPGA_3V3 3.3V
C
f
C
f
VCC3V3 3.3V
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
LMZ31503
U59 (1.0V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
C
f
C
f
MGTAVCC 1.0V
GPIO (Out)
FPWM (Out)
ADC (In)
ADC (In)
Input
Filter
LMZ31503
U60 (1.2V Nom)
Vin Vout
EN
FB
Rail Enable
PWM Margin
Current Sense
Voltage Sense
(2)
Rs 5mΩ
+12V
V
fb
MGTAVTT 1.2V
C
f
C
f
U64
I0B
I1B
I2B
I3B
YB
S[1:0]
FMC_ADJ_SEL[1:0]
Value
0 0
0 1
1 0
1 1
VCCO_ADJ
Output
2.5V
1.8V
3.3V
3.3V
at point of load.
(Not measued separately)
(Not measued separately)
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Xilinx AC701 Specifications

General

Brand	Xilinx
Model	AC701
Category	Motherboard
Language	English