Contents
11-12. Storing a waveform. . . . . . . . . . . . . . . . . . . . 11-94
11-13. Saving to pixel memory. .. .... ... .... .... 11-97
13-1. The sampling circuit. .. .... .... .... .... 13-3
13-2. Sequential sampling process. ............... 13-5
13-3. Acquisition with record length = 64. ........... 13-6
13-4. Acquisition with record length = 2250. .......... 13-7
13-5. Hardware block diagram. . . . . . . . . . . . . . . . . . 13-8
13-6. The probe is a part of the circuit under test. . . . . . . . . 13-12
13-7. Simplied equivalent circuit of DUT and probe.. . . . . . . 13-13
13-8. Reduced amplitude and dc oset caused by probe loading. . . 13-14
13-9. Eects of probe capacitance. .... .... .... ... 13-15
13-10. Resistive divider probe. ................. 13-18
13-11.
A
ctive
probe
.
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13-20
13-12.
Viewing a
10
Gb/s
eye
diagram
using
12
GHz
trigger
.
.
.
.
.
13-24
13-13.
12
GHz
mode
jitter
with
200
mV
p-p
sine
wave
input.
.
.
.
.
13-26
13-14.
12
GHz/Gate
mode
jitter
with
300
mV
p-p
sine
wave
input.
.
13-27
13-15.
Gating
application.
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.
13-28
13-16.
2.5
GHz
trigger
on
signal
with
pulsed
2
GHz
RF
content.
.
.
13-29
13-17.
12
GHz
trigger
on
signal
with
pulsed
10
GHz
RF
content.
.
.
13-29
13-18.
10
Gb/s
digital
eye
diagram
without
gating. .
.
.
.
.
.
.
.
13-30
13-19.
10
Gb/s
digital
eye
diagram
with
a 1ms
gating
pulse
.
.
.
.
.
13-31
13-20.
Result
of
triggering
the
low
speed
gating pulse
generator
from
the
10
Gb/s
pattern
generator
.
.
..
..
.
.
.
.
.
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.
.
13-32
Contents-13