Display
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 34
Figure 7-2. DP and eDP Connection Example on DP0 Pins
Jetson
Tegra
DPx_HPD
DPx_AUX_N
DPx_AUX_P
DPx_TXD3_N
DPx_TXD3_P
DPx_TXD2_N
DPx_TXD2_P
DPx_TXD1_N
DPx_TXD1_P
DPx_TXD0_N
DPx_TXD0_P
DP
eDP
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
10 0k Ω
VDD_3V3_SY S
10 0k
Ω
VDD_3V3_EDP
VDD_3V3_SY S
DP
Conn
.
PWR
PWR_RET
HPD
AUXN
GND
AUXP
CEC_DP
MODE
LA NE _3 N
GND
LA NE _3 P
LA NE _2 N
GND
LA NE _2 P
LA NE _1 N
GND
LA NE _1 P
LA NE _0 N
GND
LA NE _0 P
1
3
5
11
7
9
13
15
17
19
2
10
12
6
8
14
16
18
4
20
3V 3_IO_ PG
T PD4E 05U06
VDD_1V8
10 kΩ
10 kΩ
10 kΩ
Load Switch
EN
IN OUT
Lev el Shifter
1.8V 3.3V88/96
92/100
90/98
41/65
39/63
47/71
45/69
53/77
59/83
57/81
51/75
0 / 1
HDMI_DPx_TXDN3
HDMI_DPx_TXDP3
HDMI_DPx_TXDN2
HDMI_DPx_TXDP2
HDMI_DPx_TXDN1
HDMI_DPx_TXDP1
HDMI_DPx_TXDN0
HDMI_DPx_TXDP0
DP_AUX_CHx_N
DP_AUX_CHx_P
DP_AUX_CHx_HPD
Notes:
• Level shifter required on DPx_HPD to avoid the pin from being driven when Jetson TX2 NX is
off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the
display). The reference design uses a BJT level shifter and a resistor divider is needed. See the
reference design if a similar approach will be used.
• Load Switch enable is from powergood pin of main 3.3V supply.
7.2.1.1 eDP and DP Routing Guidelines
Figure 7-3 shows the eDP/DP topology, and Table 7-7 provides the eDP and DP signal routing
requirements.
Figure 7-3. eDP Differential Main Link Topology
Jetson
eDP
Conn
Tegra
Pkg
DP
Dri ver
P
N
Com m on Mode
Cho kes & ES D